TM4C1233E6PM Datasheet, PDF (1114/1214 Pages) Texas Instruments – Tiva Microcontroller

Universal Serial Bus (USB) Controller
Register 65: USB Receive Control and Status Endpoint 1 High (USBRXCSRH1),
offset 0x117
Register 66: USB Receive Control and Status Endpoint 2 High (USBRXCSRH2),
offset 0x127
Register 67: USB Receive Control and Status Endpoint 3 High (USBRXCSRH3),
offset 0x137
Register 68: USB Receive Control and Status Endpoint 4 High (USBRXCSRH4),
offset 0x147
Register 69: USB Receive Control and Status Endpoint 5 High (USBRXCSRH5),
offset 0x157
Register 70: USB Receive Control and Status Endpoint 6 High (USBRXCSRH6),
offset 0x167
Register 71: USB Receive Control and Status Endpoint 7 High (USBRXCSRH7),
offset 0x177
USBRXCSRHn is an 8-bit register that provides additional control and status bits for transfers
through the currently selected receive endpoint.
USB Receive Control and Status Endpoint n High (USBRXCSRHn)
Base 0x4005.0000
Offset 0x117
Type RW, reset 0x00
7
6
5
4
3
2
1
0
AUTOCL ISO DMAEN
DMAMOD
reserved
Type RW
RW
RW
RW
RW
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
Bit/Field
7
Name
AUTOCL
Type
RW
Reset
0
Description
Auto Clear
Value Description
0 No effect.
1 Enables the RXRDY bit to be automatically cleared when a packet
of USBRXMAXPn bytes has been unloaded from the receive
FIFO. When packets of less than the maximum packet size are
unloaded, RXRDY must be cleared manually. Care must be taken
when using µDMA to unload the receive FIFO as data is read
from the receive FIFO in 4 byte chunks regardless of the value
of the MAXLOAD field in the USBRXMAXPn register, see “DMA
Operation” on page 1075.
1114
Texas Instruments-Production Data
June 12, 2014