TM4C1233E6PM Datasheet, PDF (608/1214 Pages) Texas Instruments – Tiva Microcontroller

Micro Direct Memory Access (μDMA)
Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500
Each bit of the DMACHASGN register represents the corresponding µDMA channel. Setting a bit
selects the secondary channel assignment as specified in Table 9-1 on page 561.
Note:
This register is provided to support legacy software. New software should use the
DMACHMAPn registers. If a bit is clear in this register, the corresponding field in the
DMACHMAPn registers is configured to 0x0. If a bit is set in this register, the corresponding
field is configured to 0x1. If this register is read, a bit reads as 0 if the corresponding
DMACHMAPn register field value is equal to 0, otherwise it reads as 1 if the corresponding
DMACHMAPn register field value is not equal to 0.
DMA Channel Assignment (DMACHASGN)
Base 0x400F.F000
Offset 0x500
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CHASGN[n]
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CHASGN[n]
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit/Field
31:0
Name
CHASGN[n]
Type
RW
Reset
-
Description
Channel [n] Assignment Select
Value Description
0 Use the primary channel assignment.
1 Use the secondary channel assignment.
608
June 12, 2014
Texas Instruments-Production Data