TM4C1233E6PM Datasheet, PDF (725/1214 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1233E6PM Microcontroller
Register 8: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x020
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
WUEMIS
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
Type RO
Reset
0
14
13
reserved
RO
RO
0
0
12
11
10
9
8
7
6
5
4
3
2
1
0
TBMMIS CBEMIS CBMMIS TBTOMIS
reserved
TAMMIS RTCMIS CAEMIS CAMMIS TATOMIS
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:17
16
Name
reserved
WUEMIS
Type
RO
RO
Reset
0x0000
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
32/64-Bit Wide GPTM Write Update Error Masked Interrupt Status
Value Description
0 An unmasked Write Update Error has not occurred.
1 An unmasked Write Update Error has occurred.
15:12
11
reserved
TBMMIS
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RO
0
GPTM Timer B Match Masked Interrupt
Value Description
0 A Timer B Mode Match interrupt has not occurred or is masked.
1 An unmasked Timer B Mode Match interrupt
has occurred.
This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR
register.
June 12, 2014
725
Texas Instruments-Production Data