TM4C123GH6PZ Datasheet, PDF (998/1446 Pages) Texas Instruments – Tiva Microcontroller

Synchronous Serial Interface (SSI)
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared on reset.
On a read, this register gives the current value of the mask on the corresponding interrupt. Setting
a bit clears the mask, enabling the interrupt to be sent to the interrupt controller. Clearing a bit sets
the corresponding mask, preventing the interrupt from being signaled to the controller.
SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x014
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TXIM RXIM RTIM RORIM
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
Name
reserved
TXIM
Type
RO
RW
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Transmit FIFO Interrupt Mask
Value Description
0 The transmit FIFO interrupt is masked.
1 The transmit FIFO interrupt is not masked.
2
RXIM
RW
0
SSI Receive FIFO Interrupt Mask
Value Description
0 The receive FIFO interrupt is masked.
1 The receive FIFO interrupt is not masked.
1
RTIM
RW
0
SSI Receive Time-Out Interrupt Mask
Value Description
0 The receive FIFO time-out interrupt is masked.
1 The receive FIFO time-out interrupt is not masked.
0
RORIM
RW
0
SSI Receive Overrun Interrupt Mask
Value Description
0 The receive FIFO overrun interrupt is masked.
1 The receive FIFO overrun interrupt is not masked.
998
June 12, 2014
Texas Instruments-Production Data