TM4C123GH6PZ Datasheet, PDF (911/1446 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C123GH6PZ Microcontroller
Register 62: ADC Clock Configuration (ADCCC), offset 0xFC8
The ADCCC register controls the clock source for the ADC module.
To use the PIOSC to clock the ADC, first power up the PLL and then enable the PIOSC in the CS
bit field, then disable the PLL.
To use the MOSC to clock the ADC, first power up the PLL and then enable the clock to the ADC
module, then disable the PLL and switch to the MOSC for the system clock.
ADC Clock Configuration (ADCCC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xFC8
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CS
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3:0
Name
reserved
CS
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RW
0
ADC Clock Source
The following table specifies the clock source that generates the ADC
clock input, see Figure 5-5 on page 222.
Value Description
0x0
Either the 16-MHz system clock (if the PLL bypass is in
effect) or the 16 MHz clock derived from PLL ÷ 25 (default).
Note that when the PLL is bypassed, the system clock must
be at least 16 MHz.
0x1
PIOSC
The PIOSC provides a 16-MHz clock source for the ADC.
If the PIOSC is used as the clock source, the ADC module
can continue to operate in Deep-Sleep mode.
0x2 - 0xF Reserved
June 12, 2014
911
Texas Instruments-Production Data