TM4C123GH6PZ Datasheet, PDF (949/1446 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C123GH6PZ Microcontroller
Bit/Field
9
8
7
6
5
Name
BERIS
PERIS
FERIS
RTRIS
TXRIS
Type
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
Description
UART Break Error Raw Interrupt Status
Value Description
0 No interrupt
1 A break error has occurred.
This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register.
UART Parity Error Raw Interrupt Status
Value Description
0 No interrupt
1 A parity error has occurred.
This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register.
UART Framing Error Raw Interrupt Status
Value Description
0 No interrupt
1 A framing error has occurred.
This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register.
UART Receive Time-Out Raw Interrupt Status
Value Description
0 No interrupt
1 A receive time out has occurred.
This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register.
For receive timeout, the RTIM bit in the UARTIM register must be set
to see the RTRIS status.
UART Transmit Raw Interrupt Status
Value Description
0 No interrupt
1 If the EOT bit in the UARTCTL register is clear, the transmit
FIFO level has passed through the condition defined in the
UARTIFLS register.
If the EOT bit is set, the last bit of all transmitted data and flags
has left the serializer.
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register
or by writing data to the transmit FIFO until it becomes greater than the
trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO
is disabled.
June 12, 2014
949
Texas Instruments-Production Data