TM4C123GH6PZ Datasheet, PDF (1221/1446 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C123GH6PZ Microcontroller
OTG A /
Host
OTG B /
Device
Register 168: USB External Power Control Interrupt Status and Clear
(USBEPCISC), offset 0x40C
This 32-bit register specifies the masked interrupt status of the two-pin external power interface. It
also provides a method to clear the interrupt state.
USB External Power Control Interrupt Status and Clear (USBEPCISC)
Base 0x4005.0000
Offset 0x40C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PF
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO RW1C
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:1
0
Name
reserved
PF
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RW1C
0
USB Power Fault Interrupt Status and Clear
Value Description
0 No interrupt has occurred or the interrupt is masked.
1 The PF bits in the USBEPCRIS and USBEPCIM registers are
set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the PF bit
in the USBEPCRIS register.
June 12, 2014
Texas Instruments-Production Data
1221