TM4C123GH6PZ Datasheet, PDF (1190/1446 Pages) Texas Instruments – Tiva Microcontroller

Universal Serial Bus (USB) Controller
Bit/Field
1
Name
FIFONE
Type
RW
Reset
0
Description
FIFO Not Empty
Value Description
0 The FIFO is empty.
1 At least one packet is in the transmit FIFO.
0
TXRDY
RW
0
Transmit Packet Ready
Value Description
0 No transmit packet is ready.
1 Software sets this bit after loading a data packet into the TX
FIFO.
This bit is cleared automatically when a data packet has been
transmitted. The EPn bit in the USBTXIS register is also set at this point.
TXRDY is also automatically cleared prior to loading a second packet
into a double-buffered FIFO.
OTG B / Device Mode
USB Transmit Control and Status Endpoint n Low (USBTXCSRLn)
Base 0x4005.0000
Offset 0x112
Type RW, reset 0x00
7
6
5
4
3
2
1
0
reserved CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY
Type RO
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
Bit/Field
7
6
5
Name
reserved
CLRDT
STALLED
Type
RO
RW
RW
Reset
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clear Data Toggle
Writing a 1 to this bit clears the DT bit in the USBTXCSRHn register.
Endpoint Stalled
Value Description
0 A STALL handshake has not been transmitted.
1 A STALL handshake has been transmitted. The FIFO is flushed
and the TXRDY bit is cleared.
Software must clear this bit.
1190
Texas Instruments-Production Data
June 12, 2014