TM4C1237H6PGE Datasheet, PDF (992/1311 Pages) Texas Instruments – The revision history table notes changes made between the indicated revisions of the

Inter-Integrated Circuit (I²C) Interface
16 Inter-Integrated Circuit (I²C) Interface
The Inter-Integrated Circuit (I²C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL), and interfaces to external I²C devices such as
serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I²C
bus may also be used for system testing and diagnostic purposes in product development and
manufacturing. The TM4C1237H6PGE microcontroller includes providing the ability to communicate
(both transmit and receive) with other I²C devices on the bus.
The TM4C1237H6PGE controller includes I²C modules with the following features:
■ Devices on the I²C bus can be designated as either a master or a slave
– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
■ Four I²C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
■ Four transmission speeds:
– Standard (100 Kbps)
– Fast-mode (400 Kbps)
– Fast-mode plus (1 Mbps)
– High-speed mode (3.33 Mbps)
■ Clock low timeout interrupt
■ Dual slave address capability
■ Glitch suppression
■ Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
– Slave generates interrupts when data has been transferred or requested by a master or when
a START or STOP condition is detected
■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
992
July 17, 2013
Texas Instruments-Production Data