TM4C1237H6PGE Datasheet, PDF (667/1311 Pages) Texas Instruments – The revision history table notes changes made between the indicated revisions of the

Tiva^™ TM4C1237H6PGE Microcontroller _{(identical to LM4F132H5QD)}
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set, a weak pull-up resistor on
the corresponding GPIO signal is enabled. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 669). Write access
to this register is protected with the GPIOCR register. Bits in GPIOCR that are cleared prevent writes
to the equivalent bit in this register.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0), with the exception of
the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the
pins back to their default state.
Table 10-8. GPIO Pins With Non-Zero Reset Values
GPIO Pins
PA[1:0]
PA[5:2]
PB[3:2]
PC[3:0]
Default State
UART0
SSI0
I²C0
JTAG/SWD
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
GPIOPCTL
0x1
0x2
0x3
0x1
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware signals including the GPIO pins that can function as
JTAG/SWD signals and the NMI signal. The commit control process must be followed
for these pins, even if they are programmed as alternate functions other than JTAG/SWD
or NMI, see “Commit Control” on page 642.
Note:
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is provided for the GPIO pins that
can be used as the four JTAG/SWD pins (PC[3:0])and the NMI pin (PD7 and PF0). Writes
to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see
page 660), GPIO Pull Up Select (GPIOPUR) register (see page 667), GPIO Pull-Down
Select (GPIOPDR) register (see page 669), and GPIO Digital Enable (GPIODEN) register
(see page 672) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 674) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR)
register (see page 675) have been set.
July 17, 2013
667
Texas Instruments-Production Data