TM4C1237H6PGE Datasheet, PDF (259/1311 Pages) Texas Instruments – The revision history table notes changes made between the indicated revisions of the

Tiva^™ TM4C1237H6PGE Microcontroller _{(identical to LM4F132H5QD)}
Register 13: System Properties (SYSPROP), offset 0x14C
This register provides information on whether certain System Control properties are present on the
microcontroller.
System Properties (SYSPROP)
Base 0x400F.E000
Offset 0x14C
Type RO, reset 0x0000.1D31
31
30
29
28
27
26
25
24
23
22
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
reserved
PIOSCPDE SRAMSM SRAMLPM reserved FLASHLPM
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
1
1
1
0
1
0
0
21
20
RO
RO
0
0
5
4
reserved
RO
RO
1
1
19
18
17
16
RO
RO
RO
0
0
0
3
2
1
reserved
RO
RO
RO
0
0
0
RO
0
0
FPU
RO
1
Bit/Field
31:13
12
Name
reserved
PIOSCPDE
Type
RO
RO
Reset
0x0
0x1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PIOSC Power Down Present
This bit determines whether the PIOSCPD bit in the DSLPCLKCFG
register can be set to power down the PIOSC in Deep-sleep mode.
Value Description
0 The status of the PIOSCPD bit is ignored.
1 The PIOSCPD bit can be set to power down the PIOSC in
Deep-sleep mode.
11
SRAMSM
RO
0x1
SRAM Sleep/Deep-sleep Standby Mode Present
This bit determines whether the SRAMPM field in the SLPPWRCFG and
DSLPPWRCFG registers can be configured to put the SRAM into
Standby mode while in Sleep or Deep-sleep mode.
Value Description
0 A value of 0x1 in the SRAMPM fields is ignored.
1 The SRAMPM fields can be configured to put the SRAM into
Standby mode while in Sleep or Deep-sleep mode.
10
SRAMLPM
RO
0x1
SRAM Sleep/Deep-sleep Low Power Mode Present
This bit determines whether the SRAMPM field in the SLPPWRCFG and
DSLPPWRCFG registers can be configured to put the SRAM into Low
Power mode while in Sleep or Deep-sleep mode.
Value Description
0 A value of 0x3 in the SRAMPM fields is ignored.
1 The SRAMPM fields can be configured to put the SRAM into Low
Power mode while in Sleep or Deep-sleep mode.
July 17, 2013
259
Texas Instruments-Production Data