TM4C1237H6PGE Datasheet, PDF (198/1311 Pages) Texas Instruments – The revision history table notes changes made between the indicated revisions of the

JTAG Interface
4.3.4
4.3.4.1
4.3.4.2
4.3.4.3
Operational Considerations
Certain operational parameters must be considered when using the JTAG module. Because the
JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these
pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire
Debug, the method for switching between these two operational modes is described below.
GPIO Functionality
When the microcontroller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (DEN[3:0]
set in the Port C GPIO Digital Enable (GPIODEN) register), enabling the pull-up resistors (PUE[3:0]
set in the Port C GPIO Pull-Up Select (GPIOPUR) register), disabling the pull-down resistors
(PDE[3:0] cleared in the Port C GPIO Pull-Down Select (GPIOPDR) register) and enabling the
alternate hardware function (AFSEL[3:0] set in the Port C GPIO Alternate Function Select
(GPIOAFSEL) register) on the JTAG/SWD pins. See page 660, page 667, page 669, and page 672.
It is possible for software to configure these pins as GPIOs after reset by clearing AFSEL[3:0] in
the Port C GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or
board-level testing, this provides four more GPIOs for use in the design.
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the TM4C1237H6PGE microcontroller. If the program code loaded into flash immediately changes the
JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt
the controller before the JTAG pin functionality switches. As a result, the debugger may be locked out
of the part. This issue can be avoided with a software routine that restores JTAG functionality based
on an external or software trigger. In the case that the software routine is not implemented and the
device is locked out of the part, this issue can be solved by using the TM4C1237H6PGE Flash
Programmer "Unlock" feature. Please refer to LMFLASHPROGRAMMER on the TI web for more
information.
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is provided for the GPIO pins that can be used as the four
JTAG/SWD pins (PC[3:0])and the NMI pin (PD7 and PF0). Writes to protected bits of the GPIO
Alternate Function Select (GPIOAFSEL) register (see page 660), GPIO Pull Up Select (GPIOPUR)
register (see page 667), GPIO Pull-Down Select (GPIOPDR) register (see page 669), and GPIO
Digital Enable (GPIODEN) register (see page 672) are not committed to storage unless the GPIO
Lock (GPIOLOCK) register (see page 674) has been unlocked and the appropriate bits of the GPIO
Commit (GPIOCR) register (see page 675) have been set.
Communication with JTAG/SWD
Because the debug clock and the system clock can be running at different frequencies, care must
be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state,
the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software
should check the ACK response to see if the previous operation has completed before initiating a
new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock
(TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have
to be checked.
Recovering a "Locked" Microcontroller
Note: Performing the sequence below restores the non-volatile registers discussed in “Non-Volatile
Register Programming” on page 516 to their factory default values. The mass erase of the
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