TMS320VC5505_13 Datasheet, PDF (99/136 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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6.14.2 I2S Electrical Data/Timing
TMS320VC5505
SPRS503B – JUNE 2009 – REVISED JANUARY 2010
Table 6-31. Timing Requirements for I2S [I/O = 3.3 V, 2.8 V, and 2.5 V]⁽¹⁾ (see Figure 6-25)
NO.
1 t_c(CLK)
Cycle time, I2S_CLK
2 t_w(CLKH) Pulse duration, I2S_CLK high
3 t_w(CLKL)
Pulse duration, I2S_CLK low
t_su(RXV-
7 ^CLKH)
t_su(RXV-
CLKL)
Setup time, I2S_RX valid before
I2S CLK high (CLKPOL = 0)
Setup time, I2S_RX valid before
I2S_CLK low (CLKPOL = 1)
t_h(CLKH-
8 ^RXV)
t_h(CLKL-
RXV)
Hold time, I2S_RX valid after
I2S_CLK high (CLKPOL = 0)
Hold time, I2S_RX valid after
I2S_CLK low (CLKPOL = 1)
t_su(FSV-
9 ^CLKH)
t_su(FSV-
CLKL)
Setup time, I2S_FS valid before
I2S_CLK high (CLKPOL = 0)
Setup time, I2S_FS valid before
I2S_CLK low (CLKPOL = 1)
t_h(CLKH-
Hold time, I2S_FS valid after
10 ^FSV)
I2S_CLK high (CLKPOL = 0)
t_h(CLKL-FSV)
Hold time, I2S_FS valid after
I2S_CLK low (CLKPOL = 1)
MASTER
CV_DD = 1.05 V CV_DD = 1.3 V
MIN MAX MIN MAX
40 or
2P^{(1) (2)}
40 or
2P^{(1) (2)}
20
20
20
20
5
5
5
5
7
7
7
7
–
–
–
–
–
–
–
–
SLAVE
CV_DD = 1.05 V
MIN MAX
CV_DD = 1.3 V
MIN MAX
40 or
2P^{(1) (2)}
40 or
2P^{(1) (2)}
20
20
20
20
5
5
5
5
2
2
2
2
15
15
15
t_w(CLKH) +
0.6 ⁽³⁾
t_w(CLKL) +
0.6 ⁽³⁾
15
t_w(CLKH) +
0.6 ⁽³⁾
t_w(CLKL) +
0.6 ⁽³⁾
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) P = SYSCLK period in ns. For example, when running parts at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
(3) In Slave Mode, I2S_FS is required to be latched on both edges of I2S input clock (I2S_CLK).
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Peripheral Information and Electrical Specifications
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