TMS320VC5505_13 Datasheet, PDF (68/136 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5505
SPRS503B – JUNE 2009 – REVISED JANUARY 2010
www.ti.com
6.7.1.3 Reset Pin (RESET)
The VC5505 can receive an external reset signal on the RESET pin. As specified above in
Section 6.7.1.2, Main Power-On Reset, the RESET pin is combined with the internal POWERGOOD
signal, that is generated by the MAIN POR, via an AND-gate. The output of the AND gate provides the
hardware reset to the chip. The RESET pin may be tied high and the MAIN POR will provide the hardware
reset, or the RESET pin may be externally generated.
Once the internal hardware reset, from the MAIN POR and the RESET pin, goes high, the DSP clock
generator is enabled and the DSP starts the boot sequence. For more information on the boot sequence,
see Section 4.4, Boot Sequence.
6.7.2 Pin Behaviors at Reset
During normal operation, pins are controlled by the respective peripheral selected in the External Bus
Selection Register (EBSR) register. During power-on reset and reset, the behavior of the output pins
changes and is categorized as follows:
• ^{High Group: EM_CS4, EM_CS5, EM_CS2, EM_CS3, EM_DQM0, EM_DQM1, EM_OE, EM_WE,}
LCD_RS/SPI_CS3, RSV15, RSV14, XF
• ^{Low Group: LCD_EN_RDB/SPI_CLK, EM_R/W, MMC0_CLK/I2S0_CLK/GP[0],}
MMC1_CLK/I2S1_CLK/GP[6], RSV12
• ^{Z Group: EM_D[15:0], EMU[1:0], SCL, SDA, LCD_D[0]/SPI_RX, LCD_D[1]/SPI_TX,}
LCD_D[10]/I2S2_RX/GP[20]/SPI_RX, LCD_D[11]/I2S2_DX/GP[27]/SPI_TX,
LCD_D[12]/I2S2_RTS/GP[28]/I2S3_CLK, LCD_D[13]/I2S2_CTS/GP[29]/I2S3_RS,
LCD_D[14]/I2S2_RXD/GP[30]/I2S3_RX, LCD_D[15]/I2S2_TXD/GP[31]/I2S3_DX, LCD_D[2]/GP[12],
LCD_D[3]/GP[13], LCD_D[4]/GP[14], LCD_D[5]/GP[15], LCD_D[6]/GP[16], LCD_D[7]/GP[17],
LCD_D[8]/I2S2_CLK/GP[18]/SPI_CLK,LCD_D[9]/I2S2_FS/GP[19]/SPI_CS0, RTC_CLKOUT,
MMC0_CMD/I2S0_FS/GP[1], MMC0_D0/I2S0_DX/GP[2], MMC0_D1/I2S0_RX/GP[3],
MMC0_D2/GP[4], MMC0_D3/GP[5], MMC1_CMD/I2S1_FS/GP[7], MMC1_D0/I2S1_DX/GP[8],
MMC1_D1/I2S1_RX/GP[9], MMC1_D2/GP[10], MMC1_D3/GP[11], TDO, WAKEUP
• ^{CLKOUT Group: CLKOUT, LCD_CS1_E1/SPI_CS1}
• ^{SYNCH 0→1 Group: LCD_CS0_E0/SPI_CS0, LCD_RW_WRB/SPI_CS2, RSV13}
• ^{SYNCH 1→0 Group: RSV10, RSV11}
• ^{SYNCH X→1 Group: EM_BA[1:0]}
• ^{SYNCH X→0 Group: EM_A[20:0]}
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Peripheral Information and Electrical Specifications
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