TMS320VC5505_13 Datasheet, PDF (73/136 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5505
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SPRS503B – JUNE 2009 – REVISED JANUARY 2010
• NAND Flash memories
• NOR Flash memories
The EMIF data bus can be configured for both 8- or 16-bit width. The device supports up to 21 address
lines and four external wait/interrupt inputs. Up to four asynchronous chip selects are supported by EMIF
(EM_CS[5:2]).
Each chip select has the following individually programmable attributes:
• Data bus width
• Read cycle timings: setup, hold, strobe
• Write cycle timings: setup, hold, strobe
• Bus turn around time
• Extended Wait Option With Programmable Timeout
• Select Strobe Option
• NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes
6.9.2 EMIF Peripheral Register Description(s)
Table 6-11 shows the EMIF registers.
Table 6-11. External Memory Interface (EMIF) Peripheral Registers⁽¹⁾
HEX ADDRESS
RANGE
1000h
1001h
1004h
1005h
1010h
1011h
1014h
1015h
1018h
1019h
101Ch
101Dh
1040h
1044h
1048h
104Ch
1060h
1064h
1065h
1068h
1069h
1070h
1071h
1074h
1075h
1078h
ACRONYM
REV
STATUS
AWCCR1
AWCCR2
ACS2CR1
ACS2CR2
ACS3CR1
ACS3CR2
ACS4CR1
ACS4CR2
ACS5CR1
ACS5CR2
EIRR
EIMR
EIMSR
EIMCR
NANDFCR
NANDFSR1
NANDFSR2
PGMODECTRL1
PGMODECTRL2
NCS2ECC1
NCS2ECC2
NCS3ECC1
NCS3ECC2
NCS4ECC1
REGISTER NAME
Revision Register
Status Register
Asynchronous Wait Cycle Configuration Register 1
Asynchronous Wait Cycle Configuration Register 2
Asynchronous CS2 Configuration Register 1
Asynchronous CS2 Configuration Register 2
Asynchronous CS3 Configuration Register 1
Asynchronous CS3 Configuration Register 2
Asynchronous CS4 Configuration Register 1
Asynchronous CS4 Configuration Register 2
Asynchronous CS5 Configuration Register 1
Asynchronous CS5 Configuration Register 2
EMIF Interrupt Raw Register
EMIF Interrupt Mask Register
EMIF Interrupt Mask Set Register
EMIF Interrupt Mask Clear Register
NAND Flash Control Register
NAND Flash Status Register 1
NAND Flash Status Register 2
Page Mode Control Register 1
Page Mode Control Register 2
NAND Flash CS2 1-Bit ECC Register 1
NAND Flash CS2 1-Bit ECC Register 2
NAND Flash CS3 1-Bit ECC Register 1
NAND Flash CS3 1-Bit ECC Register 2
NAND Flash CS4 1-Bit ECC Register 1
(1) Before reading or writing to the EMIF registers, be sure to set the BYTEMODE bits to 00b in the EMIF system control register to enable
word accesses to the EMIF registers.
Copyright © 2009–2010, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
73
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