TMS320VC5505_13 Datasheet, PDF (26/136 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5505
SPRS503B – JUNE 2009 – REVISED JANUARY 2010
www.ti.com
Table 3-14. LCD Bridge Terminal Functions
SIGNAL
TYPE⁽¹⁾ OTHER^{(2) (3)} DESCRIPTION
NAME
NO.
LCD_EN_RDB/
SPI_CLK
N3
O/Z
DV_DDIO
This pin is multiplexed between LCD Bridge and SPI.
For LCD Bridge, this pin is either LCD Bridge read/write enable (MPU68 mode) or
read strobe (MPU80 mode).
Mux control via the PPMODE bits in the EBSR.
LCD_CS0_E0/
SPI_CS0
P4
I/O/Z
DV_DDIO
This pin is multiplexed between LCD Bridge and SPI.
For LCD Bridge, this pin is either LCD Bridge chip select 0 (MPU68 and MPU80
modes) or enable 0 (HD44780 mode).
Mux control via the PPMODE bits in the EBSR.
LCD_CS1_E1/
SPI_CS1
N4
I/O/Z
DV_DDIO
This pin is multiplexed between LCD Bridge and SPI.
For LCD Bridge, this pin is either LCD Bridge chip select 1 (MPU68 and MPU80
modes) or enable 1 (HD44780 mode).
Mux control via the PPMODE bits in the EBSR.
LCD_RW_WRB/
SPI_CS2
P5
I/O/Z
DV_DDIO
This pin is multiplexed between LCD Bridge and SPI.
For LCD, this pin is either LCD Bridge read/write select (HD44780 and MPU68
modes) or write strobe (MPU80 mode).
Mux control via the PPMODE bits in the EBSR,.
LCD_RS/
SPI_CS3
N5 I/O/Z
DV_DDIO
This pin is multiplexed between LCD Bridge and SPI.
For LCD, this pin is the LCD Bridge address set-up.
Mux control via the PPMODE bits in the EBSR.
LCD_D[15]/
UART_TXD/
GP[31]/
P14
I/O/Z
I2S3_DX
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For LCD Bridge, it is LCD data pin 15.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
LCD_D[14]/
UART_RXD/
GP[30]/
N13
I/O/Z
I2S3_RX
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For LCD Bridge, it is LCD data pin 14.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
LCD_D[13]/
UART_CTS/
GP[29]/
P13
I/O/Z
I2S3_FS
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For LCD Bridge, it is LCD data pin 13.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
LCD_D[12]/
UART_RTS/
GP[28]/
N12
I/O/Z
I2S3_CLK
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge, I2S2, and GPIO.
For LCD Bridge, it is LCD data pin 12.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
LCD_D[11]/
I2S2_DX/
GP[27]/
SPI_TX
P12 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
For LCD Bridge, it is LCD data pin 11.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
LCD_D[10]/
I2S2_RX/
GP[20]/
SPI_RX
N11 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
For LCD Bridge, it is LCD data pin 10.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
LCD_D[9]/
I2S2_FS/
GP[19]/
SPI_CS0
P11 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
For LCD Bridge, it is LCD data pin 9.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
LCD_D[8]/
I2S2_CLK
GP[18]/
SPI_CLK
N10 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
For LCD Bridge, it is LCD data pin 8.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
LCD_D[7]/
GP[17]
P10 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge and GPIO.
For LCD Bridge, it is LCD data pin 7.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1 , Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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