TMS320VC5505_13 Datasheet, PDF (7/136 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5505
www.ti.com
SPRS503B – JUNE 2009 – REVISED JANUARY 2010
Table 3-1. Characteristics of the VC5505 Processor (continued)
PLL Options
BGA Package
Process Technology
Product Status ⁽¹⁾
HARDWARE FEATURES
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM and SARAM in Active
Mode)
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM in Retention and
SARAM in Active Mode)
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM in Active Mode and
SARAM in Retention)
Software Programmable Multiplier
10 x 10 mm
mm
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
VC5505
0.26 mW @ 1.05 V
0.44 mW @ 1.3 V
0.23 mW @ 1.05 V
0.40 mW @ 1.3 V
0.15 mW @ 1.05 V
0.28 mW @ 1.3 V
x4 to x4099 multiplier
196-Pin BGA (ZCH)
0.09 mm
PD
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
3.2 C55x CPU
The TMS320VC5505 fixed-point digital signal processor (DSP) is based on the C55x CPU 3.3 generation
processor core. The C55x DSP architecture achieves high performance and low power through increased
parallelism and total focus on power savings. The CPU supports an internal bus structure that is
composed of one program bus, three data read buses (one 32-bit data read bus and two 16-bit data read
buses), two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These
buses provide the ability to perform up to four data reads and two data writes in a single cycle. Each DMA
controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit
multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional
16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel
activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit
(DU) of the C55x CPU.
The C55x DSP generation supports a variable byte width instruction set for improved code density. The
Instruction Unit (IU) performs 32-bit program fetches from internal or external memory, stores them in a
128-byte Instruction Buffer Queue, and queues instructions for the Program Unit (PU). The Program Unit
decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline.
Predictive branching capability avoids pipeline flushes on execution of conditional instructions calls.
For more detailed information on the CPU, see the TMS320C55x CPU 3.0 CPU Reference Guide
(literature number SWPU073).
The C55x core of the VC5505 can address 16M bytes of unified data and program space. It also
addresses 64K words of I/O space. The VC5505 includes three types of on-chip memory: 128 KB
read-only memory (ROM), 256 KB single-access random access memory (SARAM), 64 KB dual-access
random access memory (DARAM). The memory map is shown in Figure 3-1.
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