LM3S9B92_16 Datasheet, PDF (967/1403 Pages) Texas Instruments – Stellaris LM3S9B92 Microcontroller

Stellaris^® LM3S9B92 Microcontroller
Register 25: Ethernet PHY Management Register 17 – Mode Control/Status
(MR17), address 0x11
This register provides the means for controlling and observing various PHY layer modes.
Ethernet PHY Management Register 17 – Mode Control/Status (MR17)
Base 0x4004.8000
Address 0x11
Type R/W, reset 0x0002
15
14
13
12
11
10
9
8
7
6
5
4
reserved FASTRIP EDPD reserved LSQE
reserved
FASTEST
reserved
Type R/W
R/W
R/W
R/W
R/W
RO
Reset
0
0
0
0
0
0
RO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
3
2
1
0
FGLS ENON reserved
R/W
R/W
RO
R/W
0
0
1
0
Bit/Field
15
14
Name
reserved
FASTRIP
Type
R/W
R/W
Reset
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Important: ^{This bit must always be written with a 0 to ensure proper}
operation.
0
10-BASE-T Fast Mode Enable
Value Description
1 Enables PHYT_10 test mode.
0 No effect.
13
EDPD
R/W
0
Enable Energy Detect Power Down
Value Description
1 Enables the Energy Detect Power Down mode.
0 No effect.
12
reserved
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Important: ^{This bit must always be written with a 0 to ensure proper}
operation.
11
LSQE
R/W
0
Low Squelch Enable
Value Description
1 Enables a lower threshold meaning more sensitivity to the signal
levels.
0 No effect.
10:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
July 03, 2014
967
Texas Instruments-Production Data