LM3S9B92_16 Datasheet, PDF (921/1403 Pages) Texas Instruments – Stellaris LM3S9B92 Microcontroller

Stellaris^® LM3S9B92 Microcontroller
Also note that if the length of the data payload section is not a multiple of 4, the FCS field is not
aligned on a word boundary in the FIFO. However, for the RX FIFO, the beginning of the next frame
is always on a word boundary.
Table 18-3. TX & RX FIFO Organization
FIFO Word Read/Write
Sequence
Word Bit Fields
TX FIFO (Write)
RX FIFO (Read)
7:0
Data Length Least Significant Frame Length Least
Byte
Significant Byte
15:8
Data Length Most Significant Frame Length Most Significant
1st
Byte
Byte
23:16
DA oct 1
31:24
DA oct 2
7:0
DA oct 3
15:8
2nd
23:16
DA oct 4
DA oct 5
31:24
DA oct 6
7:0
SA oct 1
15:8
3rd
23:16
SA oct 2
SA oct 3
31:24
SA oct 4
7:0
SA oct 5
15:8
4th
23:16
SA oct 6
Len/Type Most Significant Byte
31:24
Len/Type Least Significant Byte
7:0
data oct n
5th to nth
15:8
23:16
data oct n+1
data oct n+2
31:24
7:0
15:8
last
23:16
31:24
data oct n+3
FCS 1^a
FCS 2^a
FCS 3^a
FCS 4^a
a. If the CRC bit in the MACTCTL register is clear, the FCS bytes must be written with the correct CRC. If the CRC bit is set,
the Ethernet Controller automatically writes the FCS bytes.
18.3.1.3
Ethernet Transmission Options
At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation
by using the DUPLEX bit in the MACTCTL register. Note that in 10BASE-T half-duplex mode, the
transmitted data is looped back on the receive path.
The Ethernet Controller automatically generates and inserts the Frame Check Sequence (FCS) at
the end of the transmit frame when the CRC bit in the MACTCTL register is set. However, for test
purposes, this feature can be disabled in order to generate a frame with an invalid CRC by clearing
the CRC bit.
The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46
bytes. The Ethernet Controller automatically pads the data section if the payload data section loaded
July 03, 2014
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