LM3S9B92_16 Datasheet, PDF (528/1403 Pages) Texas Instruments – Stellaris LM3S9B92 Microcontroller

External Peripheral Interface (EPI)
Bit/Field
0
Name
ERRRIS
Type
RO
Reset
0
Description
Error Raw Interrupt Status
The error interrupt occurs in the following situations:
■ WFIFO Full. For a full WFIFO to generate an error interrupt, the
WFERR bit in the EPIFIFOLVL register must be set.
■ Read Stalled. For a stalled read to generate an error interrupt, the
RSERR bit in the EPIFIFOLVL register must be set.
■ Timeout. If the MAXWAIT field in the EPIGPCFG register is
configured to a value other than 0, a timeout error occurs when
iRDY or XFIFO not-ready signals hold a transaction for more than
the count in the MAXWAIT field.
Value Description
0 An error has not occurred.
1 A WFIFO Full, a Read Stalled, or a Timeout error has occurred.
To determine which error occurred, read the status of the EPI Error
Interrupt Status and Clear (EPIEISC) register. This bit is cleared by
writing a 1 to the bit in the EPIEISC register that caused the interrupt.
528
July 03, 2014
Texas Instruments-Production Data