TM4C1294NCPDT Datasheet, PDF (961/1890 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1294NCPDT Microcontroller
(GPTMRIS) register). Note that the interrupt status bits are not updated by the hardware unless the
TnMIE bit in the GPTMTnMR register is set, which is different than the behavior for the time-out
interrupt. The ADC trigger is enabled by setting the TnOTE bit in GPTMCTL and the event that
activates the ADC is configured in the GPTM ADC Event (GPTMADCEV) register. The μDMA
trigger is enabled by configuring and enabling the appropriate μDMA channel as well as the type
of trigger enable in the GPTM DMA Event (GPTMDMAEV) register. See “Channel
Configuration” on page 683.
The TCACT field of the GPTM Timer n Mode (GPTMTnMR) register can be configured to clear, set
or toggle an output on a time-out event.
If software updates the GPTMTnILR or the GPTMTnPR register while the counter is counting down,
the counter loads the new value on the next clock cycle and continues counting from the new value
if the TnILD bit in the GPTMTnMR register is clear. If the TnILD bit is set, the counter loads the
new value after the next timeout. If software updates the GPTMTnILR or the GPTMTnPR register
while the counter is counting up, the timeout event is changed on the next cycle to the new value.
If software updates the GPTM Timer n Value (GPTMTnV) register while the counter is counting up
or down, the counter loads the new value on the next clock cycle and continues counting from the
new value. If software updates the GPTMTnMATCHR or the GPTMTnPMR registers, the new values
are reflected on the next clock cycle if the TnMRSU bit in the GPTMTnMR register is clear. If the
TnMRSU bit is set, the new value will not take effect until the next timeout.
If the TnSTALL bit in the GPTMCTL register is set and the RTCEN bit is not set in the GPTMCTL
register, the timer freezes counting while the processor is halted by the debugger. The timer resumes
counting when the processor resumes execution. If the RTCEN bit is set, it prevents the TnSTALL
bit from freezing the count when the processor is halted by the debugger.
The following table shows a variety of configurations for a 16-bit free-running timer while using the
prescaler. All values assume a 120-MHz clock with Tc=8.33 ns (clock period). The prescaler can
only be used when a 16/32-bit timer is configured in 16-bit mode.
Table 13-5. 16-Bit Timer With Prescaler Configurations
Prescale (8-bit value)
# of Timer Clocks (Tc)^a
00000000
1
00000001
2
00000010
3
------------
--
11111101
254
11111110
255
11111111
256
a. Tc is the clock period.
Max Time
0.548258
1.096517
1.644775
--
139.2576
139.8059
140.3541
Units
ms
ms
ms
--
ms
ms
ms
Timer Compare Action Mode
The timer compare mode is an extension to the GPTM's existing one-shot and periodic modes. This
mode can be used when an application requires a pin change state at some time in the future,
regardless of the processor state. The compare mode does not operate when the PWM mode is
active and is mutually exclusive to the PWM mode. The compare mode is enabled when the TAMR
field is set to 0x1 or 0x2 (one-shot or periodic), the TnAMS bit is 0 (capture or compare mode) and
the TCACT field is nonzero in the GPTM Timer n Mode (GPTMTnMR) register. Depending on the
TCACT encoding, the timer can perform a set, clear or toggle on the corresponding CCPn pin when
a timer match occurs. In 16-bit mode, the corresponding CCP pin can have an action applied, but
when operating in 32-bit mode, the action can only be applied to the even CCP pin.
June 18, 2014
961
Texas Instruments-Production Data