TM4C1294NCPDT Datasheet, PDF (1228/1890 Pages) Texas Instruments – Tiva Microcontroller

Quad Synchronous Serial Interface (QSSI)
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 787) to assign the QSSI signal to the specified GPIO port pin. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 742. Note
that for the QSSI module, when operating in Legacy Mode, SSInXDAT0 functions as SSInTX and
SSInXDAT1 functions as SSInRX.
Table 17-1. SSI Signals (128TQFP)
Pin Name
SSI0Clk
SSI0Fss
SSI0XDAT0
Pin Number Pin Mux / Pin
Assignment
35
PA2 (15)
36
PA3 (15)
37
PA4 (15)
Pin Type
I/O
I/O
I/O
SSI0XDAT1
38
PA5 (15)
I/O
SSI0XDAT2
SSI0XDAT3
SSI1Clk
SSI1Fss
SSI1XDAT0
40
PA6 (13)
I/O
41
PA7 (13)
I/O
120
PB5 (15)
I/O
121
PB4 (15)
I/O
123
PE4 (15)
I/O
SSI1XDAT1
124
PE5 (15)
I/O
SSI1XDAT2
SSI1XDAT3
SSI2Clk
SSI2Fss
SSI2XDAT0
125
PD4 (15)
I/O
126
PD5 (15)
I/O
4
PD3 (15)
I/O
3
PD2 (15)
I/O
2
PD1 (15)
I/O
SSI2XDAT1
1
PD0 (15)
I/O
SSI2XDAT2
SSI2XDAT3
SSI3Clk
SSI3Fss
SSI3XDAT0
SSI3XDAT1
SSI3XDAT2
SSI3XDAT3
128
PD7 (15)
I/O
127
PD6 (15)
I/O
5
PQ0 (14)
I/O
45
PF3 (14)
6
PQ1 (14)
I/O
44
PF2 (14)
11
PQ2 (14)
I/O
43
PF1 (14)
27
PQ3 (14)
I/O
42
PF0 (14)
46
PF4 (14)
I/O
118
PP0 (15)
119
PP1 (15)
I/O
Buffer Type Description
TTL
SSI module 0 clock
TTL
SSI module 0 frame signal
TTL
SSI Module 0 Bi-directional Data Pin 0 (SSI0TX in
Legacy SSI Mode).
TTL
SSI Module 0 Bi-directional Data Pin 1 (SSI0RX in
Legacy SSI Mode).
TTL
SSI Module 0 Bi-directional Data Pin 2.
TTL
SSI Module 0 Bi-directional Data Pin 3.
TTL
SSI module 1 clock.
TTL
SSI module 1 frame signal.
TTL
SSI Module 1 Bi-directional Data Pin 0 (SSI1TX in
Legacy SSI Mode).
TTL
SSI Module 1 Bi-directional Data Pin 1 (SSI1RX in
Legacy SSI Mode).
TTL
SSI Module 1 Bi-directional Data Pin 2.
TTL
SSI Module 1 Bi-directional Data Pin 3.
TTL
SSI module 2 clock.
TTL
SSI module 2 frame signal.
TTL
SSI Module 2 Bi-directional Data Pin 0 (SSI2TX in
Legacy SSI Mode).
TTL
SSI Module 2 Bi-directional Data Pin 1 (SSI2RX in
Legacy SSI Mode).
TTL
SSI Module 2 Bi-directional Data Pin 2.
TTL
SSI Module 2 Bi-directional Data Pin 3.
TTL
SSI module 3 clock.
TTL
SSI module 3 frame signal.
TTL
SSI Module 3 Bi-directional Data Pin 0 (SSI3TX in
Legacy SSI Mode).
TTL
SSI Module 3 Bi-directional Data Pin 1 (SSI3RX in
Legacy SSI Mode).
TTL
SSI Module 3 Bi-directional Data Pin 2.
TTL
SSI Module 3 Bi-directional Data Pin 3.
17.3
Functional Description
The QSSI performs serial-to-parallel conversion on data received from a peripheral device. The
CPU accesses data, control, and status information. The transmit and receive paths are buffered
1228
Texas Instruments-Production Data
June 18, 2014