TM4C1294NCPDT Datasheet, PDF (1704/1890 Pages) Texas Instruments – Tiva Microcontroller

Pulse Width Modulator (PWM)
Register 11: PWM Enable Update (PWMENUPD), offset 0x028
This register specifies when updates to the PWMnEN bit in the PWMENABLE register are performed.
The PWMnEN bit enables the pwmA' or pwmB' output to be passed to the microcontroller's pin.
Updates can be immediate or locally or globally synchronized to the next synchronous update.
PWM Enable Update (PWMENUPD)
PWM0 base: 0x4002.8000
Offset 0x028
Type RW, reset 0x0000.0000
31
30
29
28
27
26
Type
Reset
Type
Reset
RO
RO
0
0
15
14
ENUPD7
RW
RW
0
0
RO
RO
0
0
13
12
ENUPD6
RW
RW
0
0
RO
RO
0
0
11
10
ENUPD5
RW
RW
0
0
25
24
23
22
reserved
RO
RO
RO
RO
0
0
0
0
9
8
ENUPD4
RW
RW
0
0
7
6
ENUPD3
RW
RW
0
0
21
20
RO
RO
0
0
5
4
ENUPD2
RW
RW
0
0
19
18
RO
RO
0
0
3
2
ENUPD1
RW
RW
0
0
17
16
RO
RO
0
0
1
0
ENUPD0
RW
RW
0
0
Bit/Field
31:16
15:14
Name
reserved
ENUPD7
Type
RO
RW
Reset
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MnPWM7 Enable Update Mode
Value Description
0x0 Immediate
Writes to the PWM7EN bit in the PWMENABLE register are used
by the PWM generator immediately.
0x1 Reserved
0x2 Locally Synchronized
Writes to the PWM7EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0.
0x3 Globally Synchronized
Writes to the PWM7EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0 after a
synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
1704
Texas Instruments-Production Data
June 18, 2014