TMS320VC5509A_17 Datasheet, PDF (96/145 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.7.2 Synchronous DRAM (SDRAM) Timings
Table 5−9 and Table 5−10 assume testing over recommended operating conditions (see Figure 5−8 through
Figure 5−14).
Table 5−9. Synchronous DRAM Cycle Timing Requirements
NO.
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
UNIT
MIN MAX MIN MAX
M19 tsu(DV-CLKMEMH)
Setup time, read data valid before CLKMEM high
3
3
ns
M20 th(CLKMEMH-DV)
Hold time, read data valid after CLKMEM high
2
2
ns
M21 tc(CLKMEM)
Cycle time, CLKMEM
9.26†
7.52‡
ns
† _{Maximum SDRAM operating frequency = 108 MHz. Actual attainable maximum operating frequency will depend on the quality of the PC board}
design and the memory chip timing requirement.
‡ _{Maximum SDRAM operating frequency = 133 MHz. Actual attainable maximum operating frequency will depend on the quality of the PC board}
design and the memory chip timing requirement.
Table 5−10. Synchronous DRAM Cycle Switching Characteristics
NO.
PARAMETER
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
UNIT
MIN MAX MIN MAX
M22 td(CLKMEMH-CEL)
M23 td(CLKMEMH-CEH)
M24 td(CLKMEMH-BEV)
M25 td(CLKMEMH-BEIV)
M26 td(CLKMEMH-AV)
M27 td(CLKMEMH-AIV)
M28 td(CLKMEMH-SDCASL)
M29 td(CLKMEMH-SDCASH)
M30 td(CLKMEMH-DV)
M31 td(CLKMEMH-DIV)
M32 td(CLKMEMH-SDWEL)
M33 td(CLKMEMH-SDWEH)
M34 td(CLKMEMH-SDA10V)
M35 td(CLKMEMH-SDA10IV)
M36 td(CLKMEMH-SDRASL)
M37 td(CLKMEMH-SDRASH)
M38 td(CLKMEMH–CKEL)
M39 td(CLKMEMH–CKEH)
Delay time, CLKMEM high to CEx low
Delay time, CLKMEM high to CEx high
Delay time, CLKMEM high to BEx valid
Delay time, CLKMEM high to BEx invalid
Delay time, CLKMEM high to address valid
Delay time, CLKMEM high to address invalid
Delay time, CLKMEM high to SDCAS low
Delay time, CLKMEM high to SDCAS high
Delay time, CLKMEM high to data valid
Delay time, CLKMEM high to data invalid
Delay time, CLKMEM high to SDWE low
Delay time, CLKMEM high to SDWE high
Delay time, CLKMEM high to SDA10 valid
Delay time, CLKMEM high to SDA10 invalid
Delay time, CLKMEM high to SDRAS low
Delay time, CLKMEM high to SDRAS high
Delay time, CLKMEM high to CKE low
Delay time, CLKMEM high to CKE high
1.2
7
1.2
5 ns
1.2
7
1.2
5 ns
1.2
7
1.2
5 ns
1.2
7
1.2
5 ns
1.2
7
1.2
5 ns
1.2
7
1.2
5 ns
1.2
7
1.2
5 ns
1.2
7
1.2
5 ns
1.2
7
1.2
5 ns
1.2
7
1.2
5 ns
1.2
7
1.2
5 ns
1.2
7
1.2
5 ns
1.2
7
1.2
5 ns
1.2
7
1.2
5 ns
1.2
7
1.2
5 ns
1.2
7
1.2
5 ns
1.2
7
1.2
5 ns
1.2
7
1.2
5 ns
96 SPRS205K
November 2002 − Revised January 2008