TMS320VC5509A_17 Datasheet, PDF (84/145 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.3 Electrical Characteristics
5.3.1
Electrical Characteristics Over Recommended Operating Case Temperature
Range for CV_DD = 1.2 V (108 MHz) (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
DN and DP†
USBVDD = 3.0 V−3.6 V,
IOH = −300 µA
2.8
USBVDD
VOH High-level output voltage
PU
USBVDD = 3.0 V−3.6 V,
IOH = −300 µA
0.9 * USBVDD
USBVDD V
VOL
IIZ
II
IDDC
IDDP
IDDC
Low-level output voltage
Input current for outputs in
high-impedance
All other outputs
SDA & SCL‡
DN and DP†
All other outputs
Output-only or
I/O pins with bus
keepers (enabled)
DVDD = 2.7 V−3.6 V,
IOH = MAX
At 3 mA sink current
IOL = 3.0 mA
IOL = MAX
DVDD = MAX,
VO = VSS to DVDD
All other output-only
or I/O pins
Input pins with
internal pulldown
(enabled)
DVDD = MAX
VO = VSS to DVDD
DVDD = MAX,
VI = VSS to DVDD
Input current
Input pins with
internal pullup
(enabled)
DVDD = MAX,
VI = VSS to DVDD
X2/CLKIN
DVDD = MAX,
VI = VSS to DVDD
All other input-only
pins
CVDD Supply current, CPU + internal memory access§
DVDD supply current, pins active¶
CVDD supply current, standby#
Oscillator disabled.
All domains in
low-power state
DVDD = MAX,
VI = VSS to DVDD
CVDD = 1.2 V
CPU clock = 108 MHz
TC = 25_C
DVDD = 3.3 V
CPU clock = 108 MHz
TC = 25_C
CVDD = 1.2 V
TC = 25_C
0.75 * DVDD
0
−300
−5
30
−300
−50
−5
0.45
5.5
100
0.4
0.3 V
0.4
300
µA
5
300
−30
µA
50
5
mA/
MHz
mA
µA
IDDP DVDD supply current, standby
Oscillator disabled.
All domains in
low-power state.
DVDD = 3.3 V
No I/O activity
TC = 25_C
10
µA
Ci
Input capacitance
3
pF
Co
Output capacitance
3
pF
† _{USB I/O pins DP and DN can tolerate a short circuit at D+ and D− to 0 V or 5 V, as long as the recommended series resistors (see Figure 5−42)}
are connected between the D+ and DP (package), and the D− and DN (package). Do not apply a short circuit to the USB I/O pins DP and
DN in absence of the series resistors.
‡ _{The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.}
§ _{CPU executing 75% Dual MAC + 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN (DPLL) domain are active.}
All other domains are idled. See the TMS320VC5509A Power Consumption Summary Application Report (literature number SPRAA04).
¶ _{One word of a table of a 16-bit sine value is written to the EMIF every 250 ns (64 Mbps). Each EMIF output pin is connected to a 10-pF load.}
# _{In CLKGEN domain idle mode, X2/CLKIN becomes output and is driven low to stop external crystals (if used) from oscillating. Standby current}
will be higher if an external clock source tries to drive the X2/CLKIN pin during this time.
84 SPRS205K
November 2002 − Revised January 2008