TMS320VC5509A_17 Datasheet, PDF (91/145 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.6.4 Clock Generation in Lock Mode (DPLL Synthesis Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a synthesis factor of
N to generate the internal CPU clock cycle. The synthesis factor is determined by:
N=
M
D_L
where: M = the multiply factor set in the PLL_MULT field of the clock mode register
D_L = the divide factor set in the PLL_DIV field of the clock mode register
Valid values for M are (multiply by) 2 to 31. Valid values for D_L are (divide by) 1, 2, 3, and 4.
For detailed information on clock generation configuration, see the TMS320C55x DSP Peripherals Overview
Reference Guide (literature number SPRU317).
Table 5−4 and Table 5−5 assume testing over recommended operating conditions and H = 0.5t_c(CO) (see
Figure 5−4).
Table 5−4. Multiply-By-N Clock Option Timing Requirements
CVDD = 1.2 V
CVDD = 1.35 V
NO.
CVDD = 1.6 V ^UNIT
MIN MAX
C1 tc(CI)
Cycle time, X2/CLKIN
DPLL synthesis enabled
20†
400 ns
C2 tf(CI)
Fall time, X2/CLKIN
4 ns
C3 tr(CI)
Rise time, X2/CLKIN
4 ns
C10 tw(CIL)
Pulse duration, CLKIN low
6
ns
C11 tw(CIH)
Pulse duration, CLKIN high
6
ns
† _{The clock frequency synthesis factor and minimum X2/CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within}
the specified range (tc(CO)). If an external crystal is used, the X2/CLKIN cycle time is limited by the crystal frequency range listed in Table 5−1.
Table 5−5. Multiply-By-N Clock Option Switching Characteristics
NO.
PARAMETER
C4 tc(CO) Cycle time, CLKOUT
C6 tf(CO)
Fall time, CLKOUT
C7 tr(CO) Rise time, CLKOUT
C8
tw(COL)
Pulse duration, CLKOUT
low
C9
tw(COH)
Pulse duration, CLKOUT
high
Delay time, X2/CLKIN
C12 td(CI–CO) high/low to CLKOUT high/
low
‡ _{N = Clock frequency synthesis factor}
CVDD = 1.2 V
MIN TYP
MAX
9.26 tc(CI)*N‡ 1600
1
1
CVDD = 1.35 V
MIN TYP
MAX
6.95 tc(CI)*N‡ 1600
1
1
CVDD = 1.6 V
MIN TYP
MAX
5 tc(CI)*N‡ 1600
1
1
UNIT
ns
ns
ns
H−1
H+1 H−1
H+1 H−1
H + 1 ns
H−1
H+1 H−1
H+1 H−1
H + 1 ns
5 15
25
5 15
25
5 15
25 ns
November 2002 − Revised January 2008
SPRS205K
91