TMS320VC5509A_17 Datasheet, PDF (15/145 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Introduction
The TMS320C55x DSP core was created with an open architecture that allows the addition of
application-specific hardware to boost performance on specific algorithms. The hardware extensions on the
5509A strike the perfect balance of fixed function performance with programmable flexibility, while achieving
low-power consumption, and cost that traditionally has been difficult to find in the video-processor market. The
extensions allow the 5509A to deliver exceptional video codec performance with more than half its bandwidth
available for performing additional functions such as color space conversion, user-interface operations,
security, TCP/IP, voice recognition, and text-to-speech conversion. As a result, a single 5509A DSP can power
most portable digital video applications with processing headroom to spare. For more information, see the
TMS320C55x Hardware Extensions for Image/Video Applications Programmer’s Reference (literature
number SPRU098). For more information on using the the DSP Image Processing Library, see the
TMS320C55x Image/Video Processing Library Programmer’s Reference (literature number SPRU037).
2.2 Pin Assignments
Figure 2−1 illustrates the ball locations for the 179-pin ball grid array (BGA) package and is used in conjunction
with Table 2−1 to locate signal names and ball grid numbers.
DV_DD is the power supply for the I/O pins while CV_DD is the power supply for the core. V_SS is the ground for
both the I/O pins and the core. RCV_DD and RDV_DD are RTC module core and I/O supply, respectively. USBV_DD
is the USB module I/O (DP, DN, and PU) supply. ADV_DD is the power supply for the digital portion of the ADC.
AV_DD is the power supply for the analog part of the ADC. ADV_SS is the ground pin for the digital portion of the
ADC. AV_SS is the ground pin for the analog part of the ADC. USBPLLV_DD and USBPLLV_SS are the dedicated
supply and ground pins for the USB PLL, respectively.
2.2.1 Terminal Assignments for the GHH and ZHH Packages
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Figure 2−1. 179-Terminal GHH and ZHH Ball Grid Array (Bottom View)
November 2002 − Revised January 2008
SPRS205K
15