TLV320AIC3268 Datasheet, PDF (96/263 Pages) Texas Instruments – Low Power Stereo Audio Codec

TLV320AIC3268
SLAS953A – JANUARY 2014 – REVISED FEBRUARY 2014
AUDIO SERIAL INTERFACE 1
WCLK BCLK DIN DOUT
Audio Serial Interfaces
AUDIO SERIAL INTERFACE 2
WCLK BCLK DIN DOUT
AUDIO SERIAL INTERFACE 3
WCLK BCLK DIN DOUT
www.ti.com
Figure 82. Typical Multiple Connections to Three Audio Serial Interfaces
Each audio bus on the TLV320AIC3268 is very flexible, including left or right-justified data options, support for
I²S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible
master or slave configurability for each bus clock line, and the ability to communicate with multiple devices within
a system directly.
Each of the three audio buses of the TLV320AIC3268 can be configured for left or right-justified, I²S, DSP, or
TDM modes of operation, where communication with PCM interfaces is supported within the TDM mode. These
modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word clock and
bit clock can be independently configured in either Master or Slave mode, for flexible connectivity to a wide
variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as
either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected
ADC and DAC sampling frequencies. When configuring an audio interface for six-wire mode, the ADC and DAC
paths can operate based on separate word clocks.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode,
this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider. The number
of bit-clock pulses in a frame may need adjustment to accommodate various word-lengths as well as to support
the case when multiple TLV320AIC3268s may share the same audio bus. When configuring an audio interface
for six-wire mode, the ADC and DAC paths can operate based on separate bit clocks.
The TLV320AIC3268 also includes a feature to offset the position of start of data transfer with respect to the
word-clock. This offset can be controlled in terms of number of bit-clocks.
The TLV320AIC3268 also has the feature of inverting the polarity of the bit-clock used for transferring the audio
data as compared to the default clock polarity used. This feature can be used independently of the mode of
audio interface chosen.
The TLV320AIC3268 further includes programmability to 3-state the DOUT line during all bit clocks when valid
data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the
audio data begins, time-division multiplexing (TDM) can be accomplished, enabling the use of multiple codecs on
a single audio serial data bus. When the audio serial data bus is powered down while configured in master
mode, the terminals associated with the interface are put into a 3-state output condition.
By default, when the word-clocks and bit-clocks are generated by the TLV320AIC3268, these clocks are active
only when the codec (ADC, DAC or both) are powered up within the device. This is done to save power.
However, it also supports a feature when both the word clocks and bit-clocks can be active even when the codec
is powered down. This is useful when using the TDM mode with multiple codecs on the same bus, or when word-
clock or bit-clocks are used in the system as general-purpose clocks.
The TLV320AIC3268 contains advanced Digital Audio interfaces features to enable:
• Connections of Multiple Digital Audio interfaces
• 6-wire Digital Audio interfaces for separate uplink/downlink clocks or ADC/DAC clocks
96
Submit Documentation Feedback
Product Folder Links: TLV320AIC3268
Copyright © 2014, Texas Instruments Incorporated