TLV320AIC3268 Datasheet, PDF (199/263 Pages) Texas Instruments – Low Power Stereo Audio Codec

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TLV320AIC3268
SLAS953A – JANUARY 2014 – REVISED FEBRUARY 2014
Book 0 / Page 4 / Register 10: ASI1, WCLK and BCLK Control Register - 0x00 / 0x04 / 0x0A
(B0_P4_R10) (continued)
BIT
D4-D2
D1
D0
READ/
WRITE
R/W
R/W
R/W
RESET
VALUE
0 00
0
0
DESCRIPTION
ASI1 Bit Clock Direction Control
000: BCLK1 pin is Bit Clock input to ASI1
001: BCLK1 pin is Bit Clock output from ASI1
010-111: Reserved. Do not use.
Primary Audio Bit Clock Polarity Control
0: Default Bit Clock polarity
1: Bit Clock is inverted w.r.t. default polarity
ASI1 Bit Clock and ASI1 Word Clock Power control
0: ASI1 Bit Clock and ASI1 Word Clock buffers are powered down when the codec is powered
down or ASI 1 is inactive
1: ASI1 Bit Clock and ASI1 Word Clock buffers are powered up when they are used in clock
generation even when the codec is powered down
Book 0 / Page 4 / Register 11: ASI1, Bit Clock N Divider Input Control - 0x00 / 0x04 / 0x0B (B0_P4_R11)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
ASI1_ADC_BCLK_OUT configuration used for 6-wire mode with ADC Bit Clock as output:
0: ASI1_ADC_BCLK_OUT = ASI1_BCLK_OUT configured in B0_P4_R14_D[7:4].
1: ASI1_ADC_BCLK_OUT can be different from ASI1_BCLK_OUT and is configured in
B0_P4_R115_D[7:4].
D6
R/W
0
ASI1_ADC_WCLK_OUT configuration used for 6-wire mode with ADC Word Clock as output:
0: ASI1_ADC_WCLK_OUT = ASI1_WCLK_OUT configured in B0_P4_R14_D[3:0].
1: ASI1_WCLK_OUT can be different from ASI1_WCLK_OUT and is configured in
B0_P4_R115_D[3:0].
D5-D4
R
00
Reserved. Write only default values.
D3-D0
R/W
0000
ASI1 BDIV_CLKIN Multiplexer Control
0000: ASI1_BDIV_CLKIN = DAC_CLK
0001: ASI1_BDIV_CLKIN = DAC_MOD_CLK
0010: ASI1_BDIV_CLKIN = ADC_CLK
0011: ASI1_BDIV_CLKIN = ADC_MOD_CLK
0100: ASI1_BDIV_CLKIN = ASI1 Bit Clock Input Pin
0101: ASI1_BDIV_CLKIN = ASI2 Bit Clock Input Pin
0110: ASI1_BDIV_CLKIN = ASI3 Bit Clock Input Pin
0111: ASI1_BDIV_CLKIN = ASI1 ADC Bit Clock Input Pin (6-wire interface)
1000: ASI1_BDIV_CLKIN = ASI2 ADC Bit Clock Input Pin (6-wire interface)
1001-1111: Reserved. Do not use.
Book 0 / Page 4 / Register 12: ASI1, Bit Clock N Divider - 0x00 / 0x04 / 0x0C (B0_P4_R12)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
ASI1 BCLK N Divider Power Control
0: BCLK N divider powered down
1: BCLK N divider powered up
D6-D0
R/W
000 0001 ASI1 BCLK N Divider value
0000 0000: BCLK N divider = 128
0000 0001: BCLK N divider = 1
...
1111 1110: BCLK N divider = 126
1111 1111: BCLK N divider = 127
Book 0 / Page 4 / Register 13: ASI 1, Word Clock N Divider - 0x00 / 0x04 / 0x0D (B0_P4_R13)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
ASI1 WCLK Divider Power Control
0: Primary WCLK N divider is powered down
1: Primary WCLK N divider is powered up
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