TLV320AIC3268 Datasheet, PDF (110/263 Pages) Texas Instruments – Low Power Stereo Audio Codec

TLV320AIC3268
SLAS953A – JANUARY 2014 – REVISED FEBRUARY 2014
www.ti.com
WORD
CLOCK
LEFT CHANNELS
(1, 3, 5, 7)
RIGHT CHANNELS
(2, 4, 6, 8)
BIT
CLOCK
DATA
IN 1,
DATA
OUT 1
DATA
IN 2,
DATA
OUT 2
DATA
IN 3,
DATA
OUT 3
DATA
IN 4,
DATA
OUT 4
NNN
---
123
3210
LD1(n)
NNN
---
123
3210
LD2(n)
NNN
---
123
3210
LD₃(n)
NNN
---
123
3210
LD4(n)
NNN
---
123
3210
RD1(n)
NNN
---
123
3210
RD2(n)
NNN
---
123
3210
RD₃(n)
NNN
---
123
3210
RD4(n)
NNN
---
3
123
LD1(n+1)
NNN
---
3
123
LD2(n+1)
NNN
---
3
123
LD₃(n+1)
NNN
---
3
123
LD4(n+1)
offset1=1
offset1=1
Figure 107. I²S Timing for Multi-channel Mode, Four Data Lines with Offset1=1
For I²S multi-channel, multi-terminal mode, the programmed offset value should be less than the number of bit-
clocks per frame by at least the programmed word-length of the data.
8.3.10 miniDSP
The TLV320AIC3268 features two fully programmable miniDSP cores. The first miniDSP core is tightly coupled
to the ADC, the second miniDSP core is tightly coupled to the DAC. The algorithms for the miniDSP must be
loaded into the device after power up. The miniDSPs have direct access to the digital stereo audio stream on the
ADC and on the DAC side, offering the possibility for advanced, very-low group delay DSP algorithms. Each
miniDSP can run up to 1229 instructions on every audio sample at a 48kHz sample rate. The two cores can run
fully synchronized and can exchange data. The miniDSPs in TLV320AIC3268 enable advanced sound
enhancement algorithms on an audio device.
The TLV320AIC3268 features two fully programmable miniDSP cores and three ASI ports. The miniDSP_A is
capable of generating 8 channels of audio data, which can either be routed to the ASIs to be output from the
device or routed back to the miniDSP_D for a loopback function. Similarly the miniDSP_D can take in audio data
from multiple ASIs or the miniDSP_A.
The miniDSP_A can generate 8 channels of data called the miniDSP_A_DataOutput[1:8]. The
miniDSP_A_DataOutput[1,2,3,...,8] are also referred to as miniDSP_A_DataOutput[L1,R1,L2,...,R4]. When the
device is used in pre-programmed PRB modes only miniDSP_A_DataOutput[1:2] are generated by the device for
stereo modes and only miniDSP_A_DataOutput[1] is generated in the mono modes.
The miniDSP_D features 3 input ports called miniDSP_D_DataInput_1, miniDSP_D_DataInput_2 and
miniDSP_D_DataInput_3. The input port miniDSP_D_DataInput_1 features 8 channels,
miniDSP_D_DataInput_1[1:8], also referred to as miniDSP_D_DataInput_1[L1,R1,...,R4]. In the pre-programmed
stereo PRB modes only miniDSP_D_DataInput_1[1:2] are processed and other input ports are ignored. Similarly
for the pre-programmed mono PRB modes only miniDSP_D_DataInput[1] is processed. The input port
miniDSP_D_DataInput_2 features 2 channels called miniDSP_D_DataInput_2[1:2] also referred to as
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