TLV320AIC3268 Datasheet, PDF (121/263 Pages) Texas Instruments – Low Power Stereo Audio Codec

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TLV320AIC3268
SLAS953A – JANUARY 2014 – REVISED FEBRUARY 2014
Device Functional Modes (continued)
Line Output
• Single-ended Output Mode
• Differential Output Mode
Signal Processing
• Built-in Processing Block (PRB) Mode
• Programmable miniDSP Mode
Digital Audio Interface
Control Interface
SAR ADC
Interrupts
• WCLK and BCLK Master Mode
• WCLK and BCLK Slave Mode
• I2S Mode
• LJF Mode
• RJF Mode
• DSP Mode
• PCM Mode
• TDM Mode
• SPI Mode
• I2C Mode
• Internal Reference Mode
• External Reference Mode
• Auxiliary Voltage Measurement Mode
• Resistive Measurement Mode
• Pulsed Mode
• Level Mode
Multifunction Terminals
• Terminal Muxing
See Line Out Amplifier
Configurations for details.
See ADC Processing Blocks, DAC
Processing Blocks and for details.
See Digital Audio Interfaces for
details.
See Control Interfaces for details.
See SAR ADC for details.
See Interrupt Generation and
Diagnostic Flags for details.
See Multifunction Terminals for
details.
8.5 Programming
To enable the TLV320AIC3268 in a particular application, it needs to be comfigured or programmed. Initialization
Setup describes various configurations required to enable the device.
To enable use of miniDSP in configurable modes, PurePath tools are provided. Please contact Texas
Instruments for more details.
8.6 Register Maps
8.6.1 Register Map Summary
BOOK
NO.
0
0
0
Decimal
PAGE
NO.
REG.
NO.
0
0
0
1
0
2-3
0
0
4
0
0
5
0
0
6
0
0
7
0
0
8
0
0
9
0
0
10
0
0
11
0
0
12
0
0
13
0
0
14
BOOK
NO.
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Table 52. Summary of Register Map
Hex
PAGE
NO.
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
REG.
NO.
0x00
0x01
0x02-
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
DESCRIPTION
Page Select Register
Software Reset Register
Reserved Registers
Clock Control Register 1, Clock Input Multiplexers
Clock Control Register 2, PLL Input Multiplexer
Clock Control Register 3, PLL P and R Values
Clock Control Register 4, PLL J Value
Clock Control Register 5, PLL D Values (MSB)
Clock Control Register 6, PLL D Values (LSB)
Clock Control Register 7, PLL_CLKIN Divider
Clock Control Register 8, NDAC Divider Values
Clock Control Register 9, MDAC Divider Values
DAC OSR Control Register 1, MSB Value
DAC OSR Control Register 2, LSB Value
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