TLV320AIC3268 Datasheet, PDF (218/263 Pages) Texas Instruments – Low Power Stereo Audio Codec

TLV320AIC3268
SLAS953A – JANUARY 2014 – REVISED FEBRUARY 2014
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Book 0 / Page 4 / Register 105-106: Reserved Registers - 0x00 / 0x04 / 0x69-0x6A (B0_P4_R105-106)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
BIT
D7-D4
D3
D2
D1
D0
Book 0 / Page 4 / Register 107: Bit-Bang Input - 0x00 / 0x04 / 0x6B (B0_P4_R107)
READ/
WRITE
RESET
VALUE
DESCRIPTION
R
XXXX Reserved. Write only reset values.
R
X
GPIO4 Bit Bang Data Input (Input Buffer value also shown in B0_P4_R89_D1)
0: GPIO4 Bit Bang Data Input = 0
1: GPIO4 Bit Bang Data Input = 1
R
X
GPIO3 Bit Bang Data Input (Input Buffer value also shown in B0_P4_R88_D1)
0: GPIO3 Bit Bang Data Input = 0
1: GPIO3 Bit Bang Data Input = 1
R
X
GPIO2 Bit Bang Data Input (Input Buffer value also shown in B0_P4_R87_D1)
0: GPIO2 Bit Bang Data Input = 0
1: GPIO2 Bit Bang Data Input = 1
R
X
GPIO1 Bit Bang Data Input (Input Buffer value also shown in B0_P4_R86_D1)
0: GPIO1 Bit Bang Data Input = 0
1: GPIO1 Bit Bang Data Input = 1
Book 0 / Page 4 / Register 108-112: Reserved Registers - 0x00 / 0x04 / 0x6C-0x70 (B0_P4_R108-112)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 4 / Register 113: Bit-Bang miniDSP Output Control - 0x00 / 0x04 / 0x71 (B0_P4_R113)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R
0
Reserved. Write only reset values.
D6
R/W
0
0: Use B0_P4_R104 for bit-bang of outputs GPIO1, GPIO2, GPIO3, GPIO4 or GPIO6
1: Use miniDSP_D port for bit-bang of outputs GPIO1, GPIO2, GPIO3, GPIO4 or GPIO6
D5-D0
R
00 0000 Reserved. Write only reset values.
BIT
D7-D0
Book 0 / Page 4 / Register 114: Reserved Register - 0x00 / 0x04 / 0x72 (B0_P4_R114)
READ/
WRITE
RESET
VALUE
DESCRIPTION
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 4 / Register 115: ASI1, ADC Bit Clock and ADC Word Clock Output - 0x00 / 0x04 / 0x73
(B0_P4_R115)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D4
R/W
0000
ASI1_ADC_BCLK_OUT mux control used for 6-wire ASI1 mode with ADC Bit Clock as output:
0000: ASI1_ADC_BCLK_OUT = ASI1 Bit Clock Divider Output (ASI1_BDIV_OUT)
0001: Reserved. Do not use.
0010: ASI1_ADC_BCLK_OUT = ASI2 Bit Clock Divider Output (ASI2_BDIV_OUT)
0011: ASI1_ADC_BCLK_OUT = ASI2 Bit Clock Input (ASI2_BCLK)
0100: ASI1_ADC_BCLK_OUT = ASI3 Bit Clock Divider Output (ASI3_BDIV_OUT)
0101: ASI1_ADC_BCLK_OUT = ASI3 Bit Clock Input (ASI3_BCLK)
0110: Reserved. Do not use.
0111: ASI1_ADC_BCLK_OUT = ASI2 ADC Bit Clock Output (ASI2_ADC_BCLK)
1000-1111: Reserved. Do not use.
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