TMS320C6452 Datasheet, PDF (95/181 Pages) Texas Instruments – TMS320C6452 Digital Signal Processor

TMS320C6452
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SPRS371F – OCTOBER 2007 – REVISED APRIL 2012
6.8 Interrupts
The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user programmable. Also, the interrupt controller controls the generation
of the CPU exception, NMI, and emulation interrupts and the generation of AEG events. Table 6-27
summarizes the C64x+ interrupt controller registers and memory locations. For more details on DSP
interrupt control, see TMS320C6452 DSP Subsystem Reference Guide (literature number SPRUFB1).
DSP
INTERRUPT
EVENT NUMBER
0
1
2
3
4-8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30 -31
32
33
34
35
36
37
38
39
40
EVENT
Table 6-26. DSP Interrupt Events
INTERRUPT SOURCE
EVT0
EVT1
EVT2
EVT33
EMU_DTDMA
Reserved
EMU_RTDXRX
EMU_RTDXTX
IDMA0 EMC
IDMA1 EMC
DSPINT
I2CINT
Reserved
AEASYNCERR event
TINT2L
TINT2H
TINT3L
TINT3H
PSCINT
TPCC_GINT
SPIINT0
SPIINT1
Reserved
Reserved
Reserved
Reserved
RX_PULSE
RX_THRESH_PULSE
TX_PULSE
MISC_PULSE
UART_INT
Reserved
Reserved
Reserved
Reserved
Output of event combiner 0, for events 1 – 31
Output of event combiner 1, for events 32 – 63
Output of event combiner 2, for events 64 – 95
Output of event combiner 3, for events 96 – 127
Reserved
ECM interrupt for:
• Host scan access event
• DTDMA transfer complete event
• AET interrupt event
Reserved
RTDX receive complete event
RTDX transmit complete event
C64x+ EMC 0 event
C64x+ EMC 1 event
Host (PCI/HPI) to DSP interrupt event
I2C interrupt event
Reserved
EMIFA Error Interrupt event
Timer interrupt low event
Timer interrupt high event
Timer interrupt low event
Timer interrupt high event
PSC-ALLINT event
EDMA3 channel global completion interrupt event
SPI Interrupt
SPI Interrupt
Reserved
Reserved
Reserved
Reserved
Ethernet Subsystem RX pulse interrupt event
Ethernet Subsystem RX threshold interrupt event
Ethernet Subsystem TX pulse interrupt event
Ethernet Subsystem MISC pulse interrupt event
UART Interrupt
Reserved
Reserved
Reserved
Reserved
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Peripheral Information and Electrical Specifications
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