TMS320C6452 Datasheet, PDF (87/181 Pages) Texas Instruments – TMS320C6452 Digital Signal Processor

TMS320C6452
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SPRS371F – OCTOBER 2007 – REVISED APRIL 2012
6.7.7 Reset Controller Register
The reset type status (RSTYPE) register is the only register for the reset controller.
The RSTYPE register latches the cause of the last reset. If multiple reset sources occur simultaneously,
this register latches the highest priority reset source. The reset type status register is shown in Figure 6-9
and described in Table 6-22.
Figure 6-9. Reset Type Status Register (RSTYPE)
31
Reserved
R-0
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
16
4
3
2
1
0
SRST MRST WRST POR
R-0 R-0 R-0 R-0
Bit Field
31:4 Reserved
3 SRST
2 MRST
1 WRST
0 POR
Table 6-22. Reset Type Status Register (RSTYPE) Field Descriptions
Value
0
1
0
1
0
1
0
1
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
System reset
System Reset was not the last reset to occur.
System Reset was the last reset to occur.
Max reset
Max Reset was not the last reset to occur.
Max Reset was the last reset to occur.
Warm reset
Warm Reset was not the last reset to occur.
Warm Reset was the last reset to occur.
Power-on reset
Power-on Reset was not the last reset to occur.
Power-on Reset was the last reset to occur.
6.7.8 Pin Behaviors at Reset
During normal operation, devices pins are controlled by the selected peripheral. During device level global
reset, the pin behaviors are classified into the following Reset Groups:
• Z Group: These pins are 3-stated when a device-level global reset source (e.g., POR, RESET, or Max
Reset) is asserted. When the reset source is de-asserted, these pins remain 3-stated until configured
otherwise by their respective peripheral (after the peripheral is enabled by the PSC).
• Z/High Group: These pins are 3-stated when a device-level global reset source (e.g., POR, RESET,
or Max Reset) is asserted. When the reset source is de-asserted, these pins drive a logic High.
• Z/Low Group: These pins are 3-stated when a device-level global reset source (e.g. POR, RESET, or
Max Reset) is asserted. When the reset source is de-asserted, these pins drive a logic Low.
• DDR2 Z/High Group: These pins are 3-stated when a device-level global reset source (e.g. POR,
RESET, or Max Reset) is asserted. When the reset source is de-asserted, these pins are Driven High.
• DDR2 Low/High Group: These pins are driven Low when a device-level global reset source (e.g.
POR, RESET, or Max Reset) is asserted. When the reset source is de-asserted, these pins are Driven
High.
• DDR2 High/Low Group: These pins are driven High when a device-level global reset source (e.g.
POR, RESET, or Max Reset) is asserted. When the reset source is de-asserted, these pins are Driven
Low.
Copyright © 2007–2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
87
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