TMS320C6452 Datasheet, PDF (129/181 Pages) Texas Instruments – TMS320C6452 Digital Signal Processor

TMS320C6452
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SPRS371F – OCTOBER 2007 – REVISED APRIL 2012
Table 6-58. Switching Characteristics for Host-Port Interface Cycles^{(1) (2)}
(see Figure 6-34 through Figure 6-41)
NO.
PARAMETER
720
900
MIN
MAX
Case 1. HPIC or HPIA read
5
15
1
t_d(HSTBL-HDV)
Delay time, HSTROBE low to
DSP data valid
Case 2. HPID read with no auto-
increment ⁽³⁾
Case 3. HPID read with auto-increment
and read FIFO initially empty⁽³⁾
9 × M + 20
9 × M + 20
Case 4. HPID read with auto-increment
and data previously prefetched into the
5
15
read FIFO
2
t_{dis(HSTBH-HDV)}
Disable time, HD high-impedance from HSTROBE high
3
t_en(HSTBL-HD)
Enable time, HD driven from HSTROBE low
4
t_{d(HSTBL-HRDYH)}
Delay time, HSTROBE low to HRDY high
5
t_{d(HSTBH-HRDYH)} Delay time, HSTROBE high to HRDY high
Case 1. HPID read with no auto-
6
t_{d(HSTBL-HRDYL)}
Delay time, HSTROBE low to ^increment(3)
HRDY low
Case 2. HPID read with auto-increment
and read FIFO initially empty⁽³⁾
1
4
3
15
12
12
10 × M + 20
10 × M + 20
7
t_d(HDV-HRDYL)
34
t_d(DSH-HRDYL)
Delay time, HD valid to HRDY low
Case 1. HPIA write⁽³⁾
Delay time, HSTROBE high to
HRDY low
Case 2. HPID write with no auto-
increment ⁽³⁾
0
5 × M + 20
5 × M + 20
35
t_{d(HSTBL-HRDYL)}
Delay time, HSTROBE low to HRDY low for HPIA write and FIFO not
empty ⁽³⁾
40 × M + 20
36
t_{d(HASL-HRDYH)}
Delay time, HAS low to HRDY high
12
(1) M = SYSCLK3 period = 6/CPU clock frequency in ns.
(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(3) Assumes the HPI is accessing L2/L1 memory and no other master is accessing the same memory location.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Peripheral Information and Electrical Specifications 129
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