TMS320C6452 Datasheet, PDF (126/181 Pages) Texas Instruments – TMS320C6452 Digital Signal Processor

TMS320C6452
SPRS371F – OCTOBER 2007 – REVISED APRIL 2012
www.ti.com
Table 6-55. Switching Characteristics for I2C Timings⁽¹⁾ (see Figure 6-33)
NO.
16
t_c(SCL)
17
t_d(SCLH-SDAL)
18
t_d(SDAL-SCLL)
19
t_w(SCLL)
20
t_w(SCLH)
21
t_d(SDAV-SCLH)
22
t_v(SCLL-SDAV)
23
t_w(SDAH)
24
t_r(SDA)
PARAMETER
Cycle time, SCL
Delay time, SCL high to SDA low (for a repeated START
condition)
Delay time, SDA low to SCL low (for a START and a
repeated START condition)
Pulse duration, SCL low
Pulse duration, SCL high
Delay time, SDA valid to SCL high
Valid time, SDA valid after SCL low
Pulse duration, SDA high between STOP and START
conditions
Rise time, SDA
720
900
STANDARD
MODE
MIN MAX
10
FAST MODE
MIN MAX
2.5
UNIT
µs
4.7
0.6
µs
4
0.6
µs
4.7
1.3
µs
4
0.6
µs
250
100
ns
0
0 0.9 µs
4.7
1.3
µs
1000
20 + 0.1C_b
(2)
300
ns
25
t_r(SCL)
Rise time, SCL
1000
20 + 0.1C_b
(2)
300
ns
26
t_f(SDA)
Fall time, SDA
300
20 + 0.1C_b
(2)
300
ns
27
t_f(SCL)
Fall time, SCL
300
20 + 0.1C_b
(2)
300
ns
28
t_d(SCLH-SDAH)
Delay time, SCL high to SDA high (for STOP condition)
4
29 C_p
Capacitance for each I2C pin
10
(1) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(2) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
0.6
µs
10 pF
26
24
SDA
23
21
19
25
20
28
SCL
16
27
18
22
17
18
Stop Start
Repeated
Start
Stop
Figure 6-33. I2C Transmit Timings
126 Peripheral Information and Electrical Specifications
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