LMK04616 Datasheet, PDF (94/128 Pages) Texas Instruments – Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs

LMK04616
SNAS663 – MARCH 2017
www.ti.com
9.6.2.138 IOCTRL_SPI0
The IOCTRL_SPI0 Register provides control of the SDIO Input/Output Driver. Back to Register Map.
BIT NO.
[7]
[6:5]
[4]
[3]
[2]
[1]
FIELD
SPI_EN_THREE_WIRE_IF
RSRVD
SPI_SDIO_OUTPUT_MUTE
SPI_SDIO_OUTPUT_INV
SPI_SDIO_OUTPUT_WEAK
_DRIVE
SPI_SDIO_EN_PULLUP
[0]
SPI_SDIO_EN_PULLDOWN
Table 163. Register - 0x8D
TYPE
RW
-
RW
RW
RW
RW
RW
RESET
0
-
0
0
0
0
0
DESCRIPTION
SPI 3-Wire Selection. 1=3-Wire, 0=4-Wire. When configured
for 4 wire operation the SDO output is connected to the
STATUS1 output pad.
Reserved.
SDIO Output Mute. When SPI_SDIO_OUTPUT_MUTE is 1
the SDIO output driver is forced to 0 if it is enabled.
SDIO Output Invert. When SPI_SDIO_OUTPUT_INV is 1 the
SDIO output is inverted.
SDIO Output Weak Drive Strength. When
SPI_SDIO_OUTPUT_WEAK DRIVE is 1 the SDIO output is
configured with a low slew rate.
SPI SDIO Pull Up Enable. When SPI_SDIO_PULLUP_EN is
1 a pullup resistor is activated.
SPI SDIO Pull Down Enable. When
SPI_SDIO_PULLDWN_EN is 1 a pulldown resistor is
activated.
9.6.2.139 IOCTRL_SPI1
The IOCTRL_SPI1 Register provides control of the SCL and SCS input drivers. Back to Register Map.
BIT NO.
[7:4]
[3]
[2]
[1]
FIELD
RSRVD
SPI_SCL_EN_PULLUP
SPI_SCL_EN_PULLDOWN
SPI_SCS_EN_PULLUP
[0]
SPI_SCS_EN_PULLDOWN
Table 164. Register - 0x8E
TYPE
-
RW
RW
RW
RW
RESET
-
0
0
0
0
DESCRIPTION
Reserved.
SPI SCL Pull Up Enable. When SPI_SCL_PULLUP_EN is 1
a pullup resistor is activated.
SPI SCL Pull Down Enable. When SPI_SCL_PULLDWN_EN
is 1 a pulldown resistor is activated.
SPI SCS Pull Up Enable. When SPI_SCS_PULLUP_EN is 1
a pullup resistor is activated.
SPI SCS Pull Down Enable. When
SPI_SCS_PULLDWNEN_EN is 1 a pulldown resistor is
activated.
9.6.2.140 IOTEST_SDIO
The IOTEST_SDIO Register provides control of the SDIO driver and test features. Back to Register Map.
BIT NO.
[7]
[6]
FIELD
RSRVD
SPI_SDIO_OUTPUT_HIZ
[5]
SPI_SDIO_ENB_INSTAGE
[4]
SPI_SDIO_EN_ML_INSTAG
E
[3]
RSRVD
Table 165. Register - 0x8F
TYPE
-
RW
RW
RW
-
RESET
0
1
0
0
0
DESCRIPTION
Reserved.
SPI SDIO Output Driver High Impedance. When
SPI_SDIO_OUTPUT_HIZ is set to 1 the SDIO output driver
stage is disabled. Only when SPI_SDIO_IOTESTEN is 1.
SPI SDIO Input Stage Enable BAR. When
SPI_SDIO_INPUT_ENB is 0 the SDIO Input stage is
enabled. Whenever SPI_SDIO_INPUT_ENB is set to 1 the
SPI interface is rendered inoperable and can only be
recovered by a hardware reset.
SPI SDIO Input Stage Enable Multi-level. When
SPI_SDIO_INPUT_ENML is 1 the input stage is configured
for multi-level mode.
Reserved.
94
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