LMK04616 Datasheet, PDF (118/128 Pages) Texas Instruments – Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs

LMK04616
SNAS663 – MARCH 2017
www.ti.com
10.2 Typical Application
Normal use case of the LMK04616 device is as a dual loop jitter cleaner. This section will discuss a design
example to illustrate the various functional aspects of the LMK04616 device.
PLL1
PLL2
CLKinX
R
CLKinX*
4 inputs
N
LMK04616
Phase
Detector
PLL1
Integrated
Loop Filter
External
VCXO
Internal VCO
R
Phase
Detector
PLL2
Integrated
Loop Filter
Pre
Div
N
Divider
Device/SYSref
Clock
Divider
Digital Delay
Analog Delay
8 blocks
OSCout
OSCout*
16 Device/Sysref
Clocks
CLKoutX*
CLKoutX
CLKoutX*
CLKoutX
Copyright © 2017, Texas Instruments Incorporated
Figure 59. Simplified Functional Block Diagram for Dual-Loop Mode
10.2.1 Design Requirements
Given a remote radio head (RRU) type application which needs to clock some ADCs, DACs, FPGA, SERDES,
and an LO. The input clock is a recovered clock which needs jitter cleaning. The FPGA clock should have a
clock output on power up. A summary of clock input and output requirements are as follows:
Clock Input:
• 122.88-MHz recovered clock.
Clock Outputs:
• 1x 245.76-MHz clock for ADC
• 2x 983.04-MHz clock for DAC
• 2x 122.88-MHz clock for FPGA
• 1x 122.88-MHz clock for SERDES
It is also desirable to have the holdover feature engage if the recovered clock reference is ever lost. The
following information reviews the steps to produce this design.
If JESD204B support is also required for the clock outputs, see JEDEC JESD204B for more details.
10.2.2 Detailed Design Procedure
Design of all aspects of the LMK04616 are quite involved and software has been written to assist in part
selection and part programming. Contact TI for optimized loop filter settings based on the system requirement.
This design procedure gives a quick outline of the process.
NOTE
This information is current as of the date of the release of this data sheet. Design tools
receive continuous improvements to add features and improve model accuracy. Refer to
software instructions or training for latest features.
1. Device Selection
– The key to device selection is required VCO frequency given required output frequencies. The device
must be able to produce the VCO frequency that can be divided down to required output frequencies.
– The software design tools take the VCO frequency range into account for specific devices based on the
application's required output frequencies.
– To understand the process better, see the Detailed Description which provides more insight into the
functional blocks and programming options.
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