LMK04616 Datasheet, PDF (111/128 Pages) Texas Instruments – Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs

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LMK04616
SNAS663 – MARCH 2017
9.6.2.200 OUTCH10_JESD_CTRL1
The OUTCH10_JESD_CTRL1 Register controls Output CH10 Back to Register Map.
BIT NO.
[7:3]
[2:0]
FIELD
RSRVD
DYN_DDLY_CH10[2:0]
Table 225. Register - 0x139
TYPE
-
RW
RESET
-
0x0
DESCRIPTION
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
9.6.2.201 OUTCH11_JESD_CTRL1
The OUTCH11_JESD_CTRL1 Register controls Output CH11 Back to Register Map.
BIT NO.
[7:3]
[2:0]
FIELD
RSRVD
DYN_DDLY_CH11[2:0]
Table 226. Register - 0x13A
TYPE
-
RW
RESET
-
0x0
DESCRIPTION
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
9.6.2.202 OUTCH12_JESD_CTRL1
The OUTCH12_JESD_CTRL1 Register controls Output CH12 Back to Register Map.
BIT NO.
[7:3]
[2:0]
FIELD
RSRVD
DYN_DDLY_CH12[2:0]
Table 227. Register - 0x13B
TYPE
-
RW
RESET
-
0x0
DESCRIPTION
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
9.6.2.203 OUTCH13_JESD_CTRL1
The OUTCH13_JESD_CTRL1 Register controls Output CH13 Back to Register Map.
BIT NO.
[7:3]
[2:0]
FIELD
RSRVD
DYN_DDLY_CH13[2:0]
Table 228. Register - 0x13C
TYPE
-
RW
RESET
-
0x0
DESCRIPTION
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
9.6.2.204 OUTCH14_JESD_CTRL1
The OUTCH14_JESD_CTRL1 Register controls Output CH14 Back to Register Map.
BIT NO.
[7:3]
[2:0]
FIELD
RSRVD
DYN_DDLY_CH14[2:0]
Table 229. Register - 0x13D
TYPE
-
RW
RESET
-
0x0
DESCRIPTION
Reserved.
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
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