LMK04616 Datasheet, PDF (105/128 Pages) Texas Instruments – Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs

www.ti.com
LMK04616
SNAS663 – MARCH 2017
9.6.2.175 OUTCH10_JESD_CTRL
Register OUTCH10_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
BIT NO.
[7]
[6:2]
[1]
[0]
FIELD
RSRVD
CH10_ADLY[4:0]
CH10_ADLY_EN
RSRVD
Table 200. Register - 0x116
TYPE
-
RW
RW
-
RESET
-
0x0
0
-
DESCRIPTION
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
Enables Analog Delay for Channel 10.
Reserved.
9.6.2.176 OUTCH11_JESD_CTRL
Register OUTCH11_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
BIT NO.
[7]
[6:2]
[1]
[0]
FIELD
RSRVD
CH11_ADLY[4:0]
CH11_ADLY_EN
RSRVD
Table 201. Register - 0x117
TYPE
-
RW
RW
-
RESET
-
0x0
0
-
DESCRIPTION
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
Enables Analog Delay for Channel 11.
Reserved.
9.6.2.177 OUTCH12_JESD_CTRL
Register OUTCH12_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
BIT NO.
[7]
[6:2]
[1]
[0]
FIELD
RSRVD
CH12_ADLY[4:0]
CH12_ADLY_EN
RSRVD
Table 202. Register - 0x118
TYPE
-
RW
RW
-
RESET
-
0x0
0
-
DESCRIPTION
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
Enables Analog Delay for Channel 12.
Reserved.
9.6.2.178 OUTCH13_JESD_CTRL
Register OUTCH13_JESD_CTRL provides control of the following JESD204B control signals Back to Register
Map.
BIT NO.
[7]
[6:2]
[1]
[0]
FIELD
RSRVD
CH13_ADLY[4:0]
CH13_ADLY_EN
RSRVD
Table 203. Register - 0x119
TYPE
-
RW
RW
-
RESET
-
0x0
0
-
DESCRIPTION
Reserved.
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
Enables Analog Delay for Channel 13.
Reserved.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK04616
Submit Documentation Feedback 105