LMK04616 Datasheet, PDF (92/128 Pages) Texas Instruments – Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs

LMK04616
SNAS663 – MARCH 2017
www.ti.com
9.6.2.127 PLL2_AC_STRT_THRESHOLD
The PLL2_AC_THRESHOLD Register sets the Amplitude Calibration Starting Threshold Back to Register Map.
BIT NO.
[7:5]
[4:0]
FIELD
RSRVD
PLL2_AC_STRT_THRESHO
LD[4:0]
Table 152. Register - 0x82
TYPE
-
RESET
-
DESCRIPTION
Reserved.
RW
0x0
PLL2 VCO Amplitude Calibration Starting Threshold.
9.6.2.128 PLL2_AC_WAIT_CTRL
The PLL2_AC_WAIT_CTRL Register sets the Amplitude Calibration Wait Periods. Back to Register Map.
BIT NO.
[7:4]
FIELD
PLL2_AC_CMP_WAIT[3:0]
[3:0]
PLL2_AC_INIT_WAIT[3:0]
Table 153. Register - 0x83
TYPE
RW
RW
RESET
0x0
0x0
DESCRIPTION
PLL2 VCO Amplitude Calibration Delay between IDAC Code
Changes. Delay is equal to PLL2_AC_CMP_WAIT*4*Clock
Period (Clock Period 100ns).
PLL2 VCO Amplitude Calibration Initial Comparator Delay.
Delay is equal to PLL2_AC_INIT_WAIT*4*Clock Period.
9.6.2.129 PLL2_AC_JUMPSTEP
The PLL2_AC_JUMPSTEP Register provides control of the PLL2 Amplitude Calibration step size. Back to
Register Map.
BIT NO.
[7:4]
[3:0]
FIELD
RSRVD
PLL2_AC_JUMP_STEP[3:0]
Table 154. Register - 0x84
TYPE
-
RW
RESET
-
0xF
DESCRIPTION
Reserved.
PLL2 IDAC Code Jump Step. When PLL2_FAST_ACAL is 1
then the IDACSET step value is set by
PLL2_AC_JUMP_STEP.
9.6.2.130 PLL2_LD_WNDW_SIZE
The PLL2_LD_WNDW_SIZE Register sets the PLL2 Window Comparator Setting. Back to Register Map.
BIT NO.
[7:0]
FIELD
PLL2_LD_WNDW_SIZE[7:0]
Table 155. Register - 0x85
TYPE
RW
RESET
0x1
DESCRIPTION
PLL2 Window Comparator Size Setting. PLL2 Window
comparator size after PLL2 AC Calibration and initial lock.
9.6.2.131 PLL2_LD_WNDW_SIZE_INITIAL
The PLL2_LD_WNDW_SIZE_INITIAL Register sets the PLL2 Window Comparator Initial Setting. Back to
Register Map.
BIT NO.
[7:0]
FIELD
PLL2_LD_WNDW_SIZE_INI
TIAL[7:0]
Table 156. Register - 0x86
TYPE
RW
RESET
0x7F
DESCRIPTION
PLL2 Window Comparator Size Initial Setting. Window
comparator size prior to PLL2 AC Calibration and initial lock.
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