TMS320DM368_17 Datasheet, PDF (93/208 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM368
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SPRS668C – APRIL 2010 – REVISED JUNE 2011
EDMA
CHANNEL
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Table 6-16. EDMA Channel Synchronization Events^{(1) (2)} (continued)
EVENT NAME
EVENT DESCRIPTION
TIMER1: TEVT2
Timer 2(TEVT2) Event
TIMER1: TEVT3
Timer 3(TEVT3) Event
PWM0
PWM 0 Event
PWM1 or MJCP : IMX1INT
PWM 1 Event or MJCP IMX1INT interrupt
PWM2 or MJCP : NSFINT
PWM 2 Event or MJCP NSFINT interrupt
PWM3 or HDVICP(6) :
CP_UNDEF
MPEG/JPEG Coprocessor PWM 3 Event or High Definition Video Image Coprocessor
CP_UNDEF Event
MJCP : VLCDINT or
HDVICP(5) : CP_ECDCMP
MPEG/JPEG Coprocessor VLCDINT Event or High Definition Video Image Coprocessor
CP_ECDCMP Event
MJCP : BIMINT or
HDVICP(8) : CP_ME
MPEG/JPEG Coprocessor BIMINT Event or High Definition Video Image Coprocessor
CP_ME Event
MJCP : DCTINT or
HDVICP(1) : CP_CALC
MPEG/JPEG Coprocessor DCTINT Event or High Definition Video Image Coprocessor
CP_CALC Event
MJCP : QIQINT or
HDVICP(7) : CP_IPE
MPEG/JPEG Coprocessor QIQINT Event or High Definition Video Image Coprocessor
CP_IPE Event
MJCP : BPSINT or
HDVICP(2) : CP_BS
MPEG/JPEG Coprocessor BPSINT Event or High Definition Video Image Coprocessor
CP_BS Event
MJCP : VLCDERRINT or MPEG/JPEG Coprocessor VLCDERRINT Event or High Definition Video Image Coprocessor
HDVICP(0) : CP_LPF
CP_LPF Event
MJCP : RCNTINT or
HDVICP(3) : CP_MC
MPEG/JPEG Coprocessor RCNTINT Event or High Definition Video Image Coprocessor
CP_MC Event
MJCP : COPCINT or
HDVICP(4) : CP_ECDEND
MPEG/JPEG Coprocessor COPCINT Event or High Definition Video Image Coprocessor
CP_ECDEND Event
6.9.2 EDMA Peripheral Register Description(s)
Table 6-17 lists the EDMA registers, their corresponding acronyms, and device memory locations
(offsets).
Offset
00h
04h
0200h
0204h
0208h
020Ch
0210h
0214h
0218h
021Ch
0240h
0244h
0248h
024Ch
0250h
0254h
0258h
025Ch
Acronym
PID
CCCFG
QCHMAP0
QCHMAP1
QCHMAP2
QCHMAP3
QCHMAP4
QCHMAP5
QCHMAP6
QCHMAP7
DMAQNUM0
DMAQNUM1
DMAQNUM2
DMAQNUM3
DMAQNUM4
DMAQNUM5
DMAQNUM6
DMAQNUM7
Table 6-17. EDMA Registers
Register Description
Peripheral Identification Register
EDMA3CC Configuration Register
Global Registers
QDMA Channel 0 Mapping Register
QDMA Channel 1 Mapping Register
QDMA Channel 2 Mapping Register
QDMA Channel 3 Mapping Register
QDMA Channel 4 Mapping Register
QDMA Channel 5 Mapping Register
QDMA Channel 6 Mapping Register
QDMA Channel 7 Mapping Register
DMA Queue Number Register 0
DMA Queue Number Register 1
DMA Queue Number Register 2
DMA Queue Number Register 3
DMA Queue Number Register 4
DMA Queue Number Register 5
DMA Queue Number Register 6
DMA Queue Number Register 7
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Peripheral Information and Electrical Specifications
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