TMS320DM368_17 Datasheet, PDF(88/208 Page) Texas Instruments

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TMS320DM368_17 Datasheet, PDF (88/208 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

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TMS320DM368

SPRS668C â APRIL 2010 â REVISED JUNE 2011

www.ti.com

6.8.1 GPIO Peripheral Register Description(s)

Table 6-12 lists the GPIO registers, their corresponding acronyms, and device memory locations (offsets).

OFFSET

10h

14h

18h

1Ch

20h

24h

28h

2Ch

30h

34h

38h

3Ch

40h

44h

48h

60h

64h

68h

6Ch

70h

88h

8Ch

90h

94h

98h

Table 6-12. General-Purpose Input/Output (GPIO) Registers

ACRONYM

PID

BINTEN

DIR01

OUT_DATA01

SET_DATA01

CLR_DATA01

IN_DATA01

SET_RIS_TRIG

CLR_RIS_TRIG

SET_FAL_TRIG

CLR_FAL_TRIG

INTSTAT

DIR23

OUT_DATA23

SET_DATA23

CLR_DATA23

IN_DATA23

DIR45

OUT_DATA45

SET_DATA45

CLR_DATA45

IN_DATA45

DIR6

OUT_DATA6

SET_DATA6

CLR_DATA6

IN_DATA6

Peripheral Identification Register

GPIO Interrupt Per-Bank Enable Register

GPIO Banks 0 and 1

GPIO Banks 0 and 1 Direction Register

GPIO Banks 0 and 1 Output Data Register

GPIO Banks 0 and 1 Set Data Register

GPIO Banks 0 and 1 Clear Data Register

GPIO Banks 0 and 1 Input Data Register

GPIO Set Rising Edge Interrupt Register

GPIO Clear Rising Edge Interrupt Register

GPIO Set Falling Edge Interrupt Register

GPIO Clear Falling Edge Interrupt Register

GPIO Interrupt Status Register

GPIO Banks 2 and 3

GPIO Banks 2 and 3 Direction Register

GPIO Banks 2 and 3 Output Data Register

GPIO Banks 2 and 3 Set Data Register

GPIO Banks 2 and 3 Clear Data Register

GPIO Banks 2 and 3 Input Data Register

GPIO Bank 4 and 5

GPIO Bank 4 and 5 Direction Register

GPIO Bank 4 and 5 Output Data Register

GPIO Bank 4 and 5 Set Data Register

GPIO Bank 4 and 5 Clear Data Register

GPIO Bank 4 and 5 Input Data Register

GPIO Bank 6

GPIO Bank 6 Direction Register

GPIO Bank 6 Output Data Register

GPIO Bank 6 Set Data Register

GPIO Bank 6 Clear Data Register

GPIO Bank 6 Input Data Register

6.8.2 GPIO Peripheral Input/Output Electrical Data/Timing

Table 6-13. Timing Requirements for GPIO Inputs (see Figure 6-11)

DEVICE

NO.

UNIT

MIN MAX

tw(GPIH)

tw(GPIL)

Pulse duration, GPIx high

Pulse duration, GPIx low

12P (1)

(1) P = PLLC1.SYSCLK4 period, where SYSCLK4 is an output clock of PLLC1. For more details, see Section 3.3, Device Clocking.

Peripheral Information and Electrical Specifications

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