TMS320DM368_17 Datasheet, PDF (58/208 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM368
SPRS668C – APRIL 2010 – REVISED JUNE 2011
www.ti.com
OSCIN
Pre-DIV
(Programmable)
Figure 3-3. PLLC1 Configuration
PLLEN
PLLDIV1*
PLL
Post-DIV
(Programmable)
1
PLLDIV2*
PLLM
(Programmable)
0
PLLDIV3*
PLLDIV4*
SYSCLK1 (USB Reference Clock)
SYSCLK2 (ARM926EJ-S, HDVICP
Block Clock)
SYSCLK3 (MJCP and HDVICP
Coprocessors Bus Interface Clock)
SYSCLK4 (Config Bus, Peripheral System
Interfaces, EDMA)
PLLDIV5*
SYSCLK5 (VPSS)
PLLDIV6*
SYSCLK6 (VENC Clock)
PLLDIV7*
SYSCLK7 (DDR 2x Clock)
PLLDIV8*
SYSCLK8 (MMC/SD0 Clock)
PLLDIV9*
BPDIV*
OSCDIV1*
SYSCLK9 (CLKOUT 2)
SYSCLKBP ( USB Reference Clock)
OBSCLK (CLKOUT0)
* – Programmable
3.3.4 PLLC2
PLLC2 provides the USB reference clock, ARM926EJ-S, DDR 2x clock, Voice Codec clock and VENC
27MHz, 74.25MHz clock. The PLLC2 functionality can be programmed via the PLLC2 registers. The
following list, Table 3-3, and Figure 3-4 describe the customization of PLLC2.
The PLLC2 customization includes the following features:
• PLLC2 provides DDR PHY, USB reference clock , ARM926EJ-S clock, VENC 27MHz, 74.25Hz clock
and Voice codec clock
• Software configurable
• Accepts clock input or internal oscillator input (the same input as PLLC1)
• PLL pre-divider value is programmable
• PLL multiplier value is programmable
• PLL post-divider value is programmable
• Only SYSCLK [5:1] are used
Table 3-3. PLLC2 Output Clocks
PLLC2SYSCLKy
PLLC2SYSCLK1
PLLC2SYSCLK2
PLLC2SYSCLK3
Used by
USB reference clock⁽¹⁾
ARM926EJ-S, HDVICP block clock ⁽¹⁾
DDR 2x clock ⁽¹⁾
PLLC2SYSCLK4
PLLC2SYSCLK5
Voice Codec clock
VENC clock ⁽¹⁾
PLLC2OBSCLK
CLKOUT1
(1) These clock outputs are multiplexed with other clocks.
PLLDIV Divider
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
58
Device Configurations
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