TMS320DM368_17 Datasheet, PDF (176/208 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM368
SPRS668C – APRIL 2010 – REVISED JUNE 2011
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CLKSTP = 11b, CLKXP = 0
NO.
M39
M40
t_su(DRV-CKXH)
t_h(CKXH-DRV)
Table 6-76. McBSP as SPI Timing Requirements
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
MASTER
MIN
MAX
16
1
UNIT
ns
ns
Table 6-77. McBSP as SPI Switching Characteristics^{(1) (2)}
CLKSTP = 11b, CLKXP = 0 (see Figure 6-51)
NO.
PARAMETER
MASTER
MIN
UNIT
MAX
M42
M34
M35
M36
M37
tc(CKX)
t_d(CKXL-FXH)
t_d(FXL-CKXH)
t_d(CKXL-DXV)
t_{dis(CKXL-DXHZ)}
Cycle time, CLKX
Delay time, CLKX low to FSX high⁽³⁾
Delay time, FSX low to CLKX high⁽⁴⁾
Delay time, CLKX low to DX valid
Disable time, DX high impedance following last data bit from
CLKX low
38.5 or 2P
ns
CLKXP - 2 CLKXP + 4 ns
CLKXP - 2 CLKXP + 2 ns
-2
6 ns
-3
8 ns
M38 t_d(FXL-DXV)
Delay time, FSX low to DX valid
CLKXH - 2 CLKXH + 10 ns
(1) P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 3.3).
(2) T = CLKX period = (1 + CLKGDV) × 2P
L₁ = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × 2P when CLKGDV is even
H₁ = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × 2P when CLKGDV is even
(3) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
(4) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
CLKX
FSX
DX
DR
M34
M35
M42
M37
Bit 0
Bit 0
M38
M39
Bit(n-1)
Bit(n-1)
M36
(n-2)
M40
(n-2)
(n-3)
(n-3)
Figure 6-51. McBSP as SPI: CLKSTP = 11b, CLKXP = 0
(n-4)
(n-4)
176 Peripheral Information and Electrical Specifications
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