TMS320F243_15 Datasheet, PDF (90/122 Pages) Texas Instruments – DSP CONTROLLERS

TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064D − DECEMBER 1997 − REVISED FEBRUARY 2006
PARAMETER MEASUREMENT INFORMATION
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
1
2
3
4
5
SPISIMO
Master Out Data Is Valid
SPISOMI
8
9
Master In Data
Must Be Valid
SPISTE†
† _{The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active}
until the SPI communication stream is complete.
Figure 33. SPI Master Mode External Timing (Clock Phase = 0)
90
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