TMS320F243_15 Datasheet, PDF (27/122 Pages) Texas Instruments – DSP CONTROLLERS

description of shared I/O pins (continued)
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064D − DECEMBER 1997 − REVISED FEBRUARY 2006
PIN NO.
144
68
64
PQFP PLCC QFP
F243
F241
56
54
43
58
55
44
83
66
55
123
15
8
121
14
7
119
13
6
102
7
64
100
6
63
Table 8. Shared Pin Configurations
MUX CONTROL
REGISTER
(name.bit #)
PIN FUNCTION SELECTED
(OCRx.n = 1)
(OCRx.n = 0)
I/O PORT DATA AND DIRECTION†
REGISTER
DATA
BIT NO.‡
DIR
BIT NO.§
OCRA.0
SCITXD
IOPA0
PADATDIR
0
8
OCRA.1
SCIRXD
IOPA1
PADATDIR
1
9
OCRA.2
XINT1
IOPA2
PADATDIR
2
10
OCRA.3
CAP1/QEP0
IOPA3
PADATDIR
3
11
OCRA.4
CAP2/QEP1
IOPA4
PADATDIR
4
12
OCRA.5
CAP3
IOPA5
PADATDIR
5
13
OCRA.6
PWM1
IOPA6
PADATDIR
6
14
OCRA.7
PWM2
IOPA7
PADATDIR
7
15
98
5
62
OCRA.8
PWM3
IOPB0
PBDATDIR
0
8
96
4
61
OCRA.9
PWM4
IOPB1
PBDATDIR
1
9
94
3
60
OCRA.10
PWM5
IOPB2
PBDATDIR
2
10
91
2
59
OCRA.11
PWM6
IOPB3
PBDATDIR
3
11
130
19
12
OCRA.12
T1PWM/T1CMP
IOPB4
PBDATDIR
4
12
128
18
11
OCRA.13
T2PWM/T2CMP
IOPB5
PBDATDIR
5
13
85
67
56
OCRA.14
TDIR
IOPB6
PBDATDIR
6
14
87
68
57
OCRA.15
TCLKIN
IOPB7
PBDATDIR
7
15
49
50
39
55
53
42
60
56
45
62
57
46
64
58
47
66
59
48
115
11
4
113
10
3
OCRB.0
OCRB.1
OCRB.2
OCRB.3
OCRB.4
OCRB.5
OCRB.6
OCRB.7
IOPC0
XF
PCDATDIR
0
8
IOPC1
BIO
PCDATDIR
1
9
SPISIMO
IOPC2
PCDATDIR
2
10
SPISOMI
IOPC3
PCDATDIR
3
11
SPICLK
IOPC4
PCDATDIR
4
12
SPISTE
IOPC5
PCDATDIR
5
13
CANTX
IOPC6
PCDATDIR
6
14
CANRX
IOPC7
PCDATDIR
7
15
116
12
5
OCRB.8
IOPD0
CLKOUT
PDDATDIR
0
8
81
65
54
OCRB.9
XINT2/ADCSOC
IOPD1
PDDATDIR
1
9
† _{Valid only if the I/O function is selected on the pin.}
‡ _{If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from.}
§ _{If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output.}
NOTE: GPIO pins IOPD2 to IOPD7 are dedicated I/O pins in F243. These pins are not available in the F241.
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