TMS320F243_15 Datasheet, PDF (36/122 Pages) Texas Instruments – DSP CONTROLLERS

TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064D − DECEMBER 1997 − REVISED FEBRUARY 2006
external interrupts
The F243/F241 devices have four external interrupts. These interrupts include:
D XINT1. The XINT1 control register (at 7070h) provides control and status for this interrupt. XINT1 can be used
as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or as a general-purpose I/O pin. XINT1
can also be programmed to trigger an interrupt on either the rising or the falling edge.
D XINT2. The XINT2 control register (at 7071h) provides control and status for this interrupt. XINT2 can be used
as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or a general-purpose I/O pin. XINT2 can
also be programmed to trigger an interrupt on either the rising or the falling edge.
D NMI. This is a nonmaskable external interrupt.
D PDPINT. This interrupt is provided for safe operation of power converters and motor drives controlled by
the F243/F241. This maskable interrupt can put the timers and PWM output pins in high-impedance states
and inform the CPU in case of motor drive abnormalities such as overvoltage, overcurrent, and excessive
temperature rise. PDPINT is a Level 1 interrupt.
Table 11 is a summary of the external interrupt capability of the F243/F241.
EXTERNAL
INTERRUPT
XINT1
XINT2
NMI
PDPINT
Table 11. External Interrupt Types and Functions
CONTROL
REGISTER
NAME
CONTROL
REGISTER
ADDRESS
XINT1CR
7070h
XINT2CR
—
EVIMRA
7071h
—
742Ch
MASKABLE?
Yes
(Level 1 or 6)
Yes
(Level 1 or 6)
No
Yes
(Level 1)
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