TMS320F243_15 Datasheet, PDF (80/122 Pages) Texas Instruments – DSP CONTROLLERS

TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064D − DECEMBER 1997 − REVISED FEBRUARY 2006
external reference crystal/clock with PLL circuit enabled
The internal oscillator is enabled by connecting a crystal across XTAL1/CLKIN and XTAL2 pins as shown in
Figure 20a. The crystal should be in fundamental operation and parallel resonant, with an effective series
resistance of 30 Ω and a power dissipation of 1 mW; it should be specified at a load capacitance of 20 pF.
timings with the PLL circuit enabled
PARAMETER
fx
C1, C2
Input clock frequency
Load capacitance
Oscillator
CLKIN
MIN
1
1
TYP MAX UNIT
5 MHz
5 MHz
10
pF
switching characteristics over recommended operating conditions [H = 0.5 t_c(CO)] (see Figure 21)
tc(CO)
tf(CO)
tr(CO)
tw(COL)
tw(COH)
tp
PARAMETER
CLOCK MODE
Cycle time, CLKOUT
Fall time, CLKOUT
Rise time, CLKOUT
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
before PLL lock,
Transition time, PLL synchronized after PLL enabled _{CLKIN multiply by 4}
MIN
50
H −3
H −3
TYP
MAX UNIT
ns
4
ns
4
ns
H
H +3 ns
H
H +3 ns
2500tc(Cl) ns
timing requirements (see Figure 21)
tc(Cl)
tf(Cl)
tr(Cl)
tw(CIL)
tw(CIH)
Cycle time, XTAL1/CLKIN
Fall time, XTAL1/CLKIN
Rise time, XTAL1/CLKIN
Pulse duration, XTAL1/CLKIN low as a percentage of tc(Cl)
Pulse duration, XTAL1/CLKIN high as a percentage of tc(Cl)
EXTERNAL REFERENCE
CRYSTAL
5 MHz
MIN MAX UNIT
200
ns
5 ns
5 ns
40
60 %
40
60 %
XTAL1/CLKIN
CLKOUT
tw(CIH)
tc(CI)
tf(Cl)
tc(CO)
tw(COH)
tw(COL)
tw(CIL)
tr(CO)
tr(Cl)
tf(CO)
Figure 21. CLKIN-to-CLKOUT Timing for PLL Oscillator Mode, Multiply-by-4 Option with 5-MHz Clock
80
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