TMS320F243_15 Datasheet, PDF (24/122 Pages) Texas Instruments – DSP CONTROLLERS

TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064D − DECEMBER 1997 − REVISED FEBRUARY 2006
software-controlled wait-state generator
Due to the fast cycle time of the F243 devices, it is often necessary to operate with wait states to interface with
external logic or memory. For many systems, one wait state is adequate.
The software wait-state generator can be programmed to generate between 0 and 7 wait states for a given
space. Software wait states are configured through the wait-state generator register (WSGR). The WSGR
includes three 3-bit fields to configure wait states for the following external memory spaces: data space (DSWS),
program space (PSWS), and I/O space (ISWS). The wait-state generator enables wait states for a given
memory space based on the value of the corresponding three bits, regardless of the condition of the READY
signal. The READY signal can be used to generate additional wait states. All bits of the WSGR are set to 1 at
reset so that the device can operate from slow memory at reset. The WSGR register (shown in Table 3, Table 4
and Table 5) resides at I / O location FFFFh. This register should not be accessed in the F241.
Table 3. Wait-State Generator Control Register ( WSGR)
15
12
11
10
9
8
6
Reserved
BVIS
ISWS
0
R/W−11
R/W−111
LEGEND:
0 = Always read as zeros, R = Read Access, W= Write Access, − n = Value after reset
5
3
DSWS
R/W−111
2
0
PSWS
R/W−111
Table 4. Wait-State(s) Programming
PSWS, DSWS, ISWS BITS
000
001
010
011
100
101
110
111
WAIT STATES FOR PROGRAM, DATA, OR I / O
0
1
2
3
4
5
6
7
BITS
2−0
5−3
8−6
10 −9
15 −11
NAME
PSWS
DSWS
ISWS
BVIS
−
Table 5. Wait-State Generator Control Register ( WSGR)
DESCRIPTION
External program space wait states. PSWS determines that between 0 to 7 wait states are applied to all reads
and writes to off-chip program space address. The memory cycle can be further extended by using the READY
signal. The READY signal does not override the wait states generated by PSWS. These bits are set to 1 (active)
by reset (RS).
External data space wait states. DSWS determines that between 0 to 7 wait states are applied to all reads and
writes to off-chip data space. The memory cycle can be further extended by using the READY signal. The READY
signal does not override the wait states generated by DSWS. These bits are set to 1 (active) by reset (RS).
External input / output space wait state. ISWS determines that between 0 to 7 wait states are applied to all reads
and writes to off-chip I / O space. The memory cycle can be further extended by using the READY signal. The
READY signal does not override the wait states generated by ISWS. These bits are set to 1 (active) by reset (RS).
Bus visibility modes. Bits 10 and 9 allow selection of various bus visibility modes while running from internal
program and/or data memory. These modes provide a method of tracing internal bus activity. These bits are set
to 11b by reset (RS), causing internal program address and program data to be output on the external address
and data pins. See Table 6.
Reserved
24
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